Having access to a VHDL "signal" using ModelSim

[Guilherme Corręa]

Hello,

I'm just starting to use ModelSim Altera Web Edition and I'm facing
some problems when I try to access the signals defined in my VHDL code.
These signal aren't visible in the ModelSim interface after the
compilation using Quartus II, but I can see the FPGA signals.
Is there any assertion that I could do to have access to these signals?

Thanks a lot.
Guilherme Corręa.