Hash collisions

[kb33]

Hi,

I would like to know what would be the best way to implement a hash
collision provision in Verilog - using the chaining or the open
addressing method? In case of the chaining method, one would have to
make linked lists in Verilog - not sure how one can do that. Please
advise.

Thanks
kb33

 

[John_H]

"kb33" <kanchan.devarakonda@gmail.com> wrote in message
news:1158705440.892926.262430@m7g2000cwm.googlegroups.com...

Hi,

I would like to know what would be the best way to implement a hash
collision provision in Verilog - using the chaining or the open
addressing method? In case of the chaining method, one would have to
make linked lists in Verilog - not sure how one can do that. Please
advise.

Thanks
kb33

For the chaining method, how would one do it in software? With memory
locations? You can instantiate single-port and dual-port memories with ease
in most tools. The design issues include the number of required memories
and the desired frequency of operation.

I haven't done any real hashing in Verilog so I can't give you a full
response. I've considered linked lists and found that the forward/backward
links I wanted weren't terribly friendly for the fast cycle times, entry
after entry that I was looking for. If I had several cycles to work with,
one memory structure would have supported my needs.