Has anybody used IOB_DLY_ADJ with S(2:0) input?

[Svenn Are Bjerkem]

Hi,
I have a DDR input which every now and then gives me a nonfunctional implementation due to unlucky input data clocking. Thought I would try to use the variable delay input elements with the S control input, but I only got error message from map that I did not connect to IO as expected.

I have instantiated the IOB_DLY_ADJ between the top level pin name recorded in the ucf file and the input pin of the IDDR2 buffer in VHDL.

D >-- (I)IOB_DLY_ADJ(O) --> (D)IDDR2(Q0/Q1) => internal DDR

Without the IOB_DLY_ADJ the design feeds data, but sometimes I am unlucky with my timing.

In the ucf file I have
NET "D" LOC = "AB2" |IOSTANDARD = "LVTTL" |IOBDELAY = "IFD";

According to the spartan3-hdl.pdf the delay buffer is supposed to be instantiated, but maybe for some reason, the original IBUF is still used. I have not been able to find much more info on this in Xilinx docs.

--
Svenn

 

[Svenn Are Bjerkem]

I reply to myself as I asked the same question on a Xilinx forum and got an answer.

IBUF_DLY_ADJ is only available on the combinational path of the IOB. This is maybe not so obvious from the simplified IOB block diagram, but ug331 figure 10.10 and the text following it clearly states this. In my case, I will have to use the IFD_DELAY_VALUE.

--
Svenn