Hardware isssue

[chris]

Hi,

I know this isn't a VHDL code issue but I was wondering if it's better
when you use several serialised FPGAs to use the same clock signal for
the all the FPGAs (comming from a external source) or to let the clock
signal going through the FPGAs. (The main clock comes in the FPGA
number 1 from the external source, then goes through the FPGA and
comes in the FGPA number 2, and so on ..).

Regards,
Christophe

 

[Cameron, Charles B.]

chris wrote:

Hi,

I know this isn't a VHDL code issue but I was wondering if it's better
when you use several serialised FPGAs to use the same clock signal for
the all the FPGAs (comming from a external source) or to let the clock
signal going through the FPGAs. (The main clock comes in the FPGA
number 1 from the external source, then goes through the FPGA and
comes in the FGPA number 2, and so on ..).

Regards,
Christophe

Generally speaking it's desirable to minimize clock skew by passing a
single clock to all its recipients at the same time so that all inputs
are read at the same moment. A couple of factors may make this infeasible:
1. If many devices need the same clock, the capacitance of each of the
recipients sums and the time required to charge the line to the
requisite voltage level climbs, slowing down the system. A hierarchical
arrangement of current buffers can be used to address this problem.
2. If the system truly is serial in nature, as suggested by your
e-mail, then clock skew may not present the usual disadvantages. In
that case, faster operation can result if you simply pass the clock
along to subsequent serial modules in a serial fashion. This is akin to
pipelining of other kinds of signals. The effect is to increase the
potential clock rate since without serializing the clock you would have
to wait for every module to complete its functions before advancing the
clock whereas by pipelining it you can advance the clock after the first
module in the chain has finished with it.

Charles B. Cameron

 

[Brannon King]

The answer to this depends on if you are sending data one direction or both
directions. For one direction, it is better to run your clock through the
FPGAs because the odds are that your data lines are the same length as the
clock lines. That would give you an advantage on knowing exactly when your
data is going to arrive. For data going both directions between chips, I
think it is easier to run them all on the global clock. That makes it easier
to set up your data window.


"chris" <ccoutand@hotmail.com> wrote in message
news:33923a80.0312160629.6154ccad@posting.google.com...

Hi,

I know this isn't a VHDL code issue but I was wondering if it's better
when you use several serialised FPGAs to use the same clock signal for
the all the FPGAs (comming from a external source) or to let the clock
signal going through the FPGAs. (The main clock comes in the FPGA
number 1 from the external source, then goes through the FPGA and
comes in the FGPA number 2, and so on ..).

Regards,
Christophe