handling inout port in testbench

[jitendra]

hi all,
i have an inout port in my design. problem is that how can i
handle this port in testbench. if i declare this port as a wire, then
it is not getting compiledlates. & if i declare it as a reg it is
getting compiled, but then design doesnt loaded in simulation in
modelsim giving the message : error loading design.

the design is like this:-
module Shifter (Clk, EN, WR, SI, SO, Data);
input Clk, EN, WR, SI;
output SO;
inout [1:0] Data;

& the testbench is as follows
module SHIFTER_TST;
reg Clk, EN, WR, SI;
wire SO;
wire [1:0]Data; // now how to declare this Data port

 

[Andy Peters]

jitendra wrote:

hi all,
i have an inout port in my design. problem is that how can i
handle this port in testbench. if i declare this port as a wire, then
it is not getting compiledlates. & if i declare it as a reg it is
getting compiled, but then design doesnt loaded in simulation in
modelsim giving the message : error loading design.

the design is like this:-
module Shifter (Clk, EN, WR, SI, SO, Data);
input Clk, EN, WR, SI;
output SO;
inout [1:0] Data;

& the testbench is as follows
module SHIFTER_TST;
reg Clk, EN, WR, SI;
wire SO;
wire [1:0]Data; // now how to declare this Data port

It should be a wire, but I'd guess that your real problem is in the
module Shifter. Show us Shifter's entire port declaration, including
the types for the signals. Hint: use Verilog-2001 "ANSI-C style"
syntax; it greatly improves readability.

-a