S
Shiv
Guest
hello friends
I am making hamming encoder, I got its verilog code on the net but, I
am understanding its last few if any of you can help me, i will be
thankful to you..
here is the code...
`timescale 1ns/1ns
module hamm_enc(out,in,reset);
parameter n=11,k=7;
output[n-1:0] out;
input[k-1:0] in;
input reset;
reg[n-1:0] out;
integer i,j;
always@(in or reset)
begin
if (reset)
out=0;
else
begin
i=0;j=0;
while((i<n)||(j<k))
//FROM HERE I AM UNDERSTANDING WHAT THEY DID
//AND WHAT THEY WANT TO DO
begin
while (i==0||i==1||i==3||i==7)
begin
out=0;
i=i+1;
end
out=in[j];
i=i+1;
j=j+1;
end
if(^(out &11'b101_0101_0101))
out[0]=~out[0];
if(^(out &11'b110_0110_0110))
out[1]=~out[1];
if(^(out &11'b000_0111_1000))
out[3]=~out[3];
if(^(out &11'b111_1000_0000))
out[7]=~out[7];
end
end
endmodule
I am making hamming encoder, I got its verilog code on the net but, I
am understanding its last few if any of you can help me, i will be
thankful to you..
here is the code...
`timescale 1ns/1ns
module hamm_enc(out,in,reset);
parameter n=11,k=7;
output[n-1:0] out;
input[k-1:0] in;
input reset;
reg[n-1:0] out;
integer i,j;
always@(in or reset)
begin
if (reset)
out=0;
else
begin
i=0;j=0;
while((i<n)||(j<k))
//FROM HERE I AM UNDERSTANDING WHAT THEY DID
//AND WHAT THEY WANT TO DO
begin
while (i==0||i==1||i==3||i==7)
begin
out=0;
i=i+1;
end
out=in[j];
i=i+1;
j=j+1;
end
if(^(out &11'b101_0101_0101))
out[0]=~out[0];
if(^(out &11'b110_0110_0110))
out[1]=~out[1];
if(^(out &11'b000_0111_1000))
out[3]=~out[3];
if(^(out &11'b111_1000_0000))
out[7]=~out[7];
end
end
endmodule