Gyrator/regulator...

C

Clifford Heath

Guest
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
<https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf>

Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that has
quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too much
supply noise onto the line and upset the signalling. It doesn\'t matter
how big an output capacitor would be, the linear regulator would
aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For reasons
of supply headroom, I want to combine a gyrator with regulation down to
nominal 5V.

The attached circuit does this ok... but I can\'t work out why it doesn\'t
work better. The Sziklai pair is operating at a gain around 250,000, so
should be multiplying the 10uF capacitance of C3 by something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?

Clifford Heath
--- Chop with axe ---
Version 4
SHEET 1 1608 1700
WIRE 704 -80 576 -80
WIRE -480 48 -544 48
WIRE -288 48 -480 48
WIRE -144 48 -288 48
WIRE 0 48 -48 48
WIRE 80 48 0 48
WIRE 208 48 160 48
WIRE 352 48 208 48
WIRE 544 48 352 48
WIRE 576 48 576 -80
WIRE 576 48 544 48
WIRE 608 48 576 48
WIRE -544 144 -544 48
WIRE -96 160 -96 112
WIRE 0 160 0 48
WIRE 704 272 704 -80
WIRE -288 288 -288 48
WIRE -208 288 -288 288
WIRE -48 288 -48 224
WIRE -48 288 -128 288
WIRE 32 288 -48 288
WIRE 208 288 208 48
WIRE 208 288 112 288
WIRE -544 336 -544 224
WIRE 544 336 544 48
WIRE 352 352 352 48
WIRE -48 368 -48 288
WIRE 0 368 -48 368
WIRE 208 368 208 288
WIRE 208 368 64 368
WIRE 704 416 704 336
WIRE -48 432 -48 368
WIRE -48 528 -48 512
WIRE -48 544 -48 528
WIRE -544 624 -544 416
WIRE -48 624 -48 608
WIRE 352 624 352 416
WIRE 544 624 544 416
WIRE 704 624 704 496
FLAG 544 624 0
FLAG 608 48 Vout
FLAG -544 624 0
FLAG -48 624 0
FLAG 704 624 0
FLAG 352 624 0
FLAG -48 288 Vb
FLAG 0 48 Vee
FLAG -480 48 Vline
FLAG -48 528 Vz
SYMBOL res 528 320 R0
SYMATTR InstName R1
SYMATTR Value 47R
SYMBOL voltage 704 400 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -61 129 Left 2
WINDOW 3 -63 102 Left 2
SYMATTR SpiceLine Rser=10
SYMATTR InstName V1
SYMATTR Value PULSE(-2 2 0.001 1u 10u 50u 100u)
SYMBOL res -112 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 470k
SYMBOL cap 0 384 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL zener -32 608 R180
WINDOW 0 47 31 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMBOL res 176 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 3.3R
SYMBOL res 128 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage -544 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 118 Left 2
SYMATTR SpiceLine Rser=5R
SYMATTR InstName V2
SYMATTR Value 14V
SYMBOL cap 688 272 R0
SYMATTR InstName C1
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL cap 336 352 R0
SYMATTR InstName C2
SYMATTR Value 47u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL ind -560 128 R0
SYMATTR InstName L1
SYMATTR Value 22mH
SYMATTR SpiceLine Rser=0.1
SYMBOL npn -96 224 R270
WINDOW 0 -7 4 VRight 2
WINDOW 3 73 6 VRight 2
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL pnp -48 112 M270
WINDOW 0 -7 86 VLeft 2
WINDOW 3 81 94 VLeft 2
SYMATTR InstName Q1
SYMATTR Value 2N5401
SYMBOL res -64 416 R0
SYMATTR InstName R2
SYMATTR Value 47k
TEXT -416 624 Left 2 !.tran 60m
TEXT -232 752 Left 2 ;HomeBus Gyrator/Regulator
TEXT 648 664 Left 2 ;Load variation
TEXT 568 432 Left 2 ;DC load
TEXT -568 672 Left 2 ;HomeBus source
 
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that has
quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too much
supply noise onto the line and upset the signalling. It doesn\'t matter
how big an output capacitor would be, the linear regulator would
aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For reasons
of supply headroom, I want to combine a gyrator with regulation down to
nominal 5V.

The attached circuit does this ok... but I can\'t work out why it doesn\'t
work better. The Sziklai pair is operating at a gain around 250,000, so
should be multiplying the 10uF capacitance of C3 by something in that
order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?

Clifford Heath
Click to expand...

I don\'t know how to fix it off hand but the rejection at 10kHz from V1
to V2 kinda sucks:

<https://imgur.com/a/w6p7Y37>

But the rejection from V2 to V1 at 10k is quite good:

<https://imgur.com/a/Sloh0I7>

I believe this gyrator structure only works well in one direction. The
wrong one.
 
On 11/9/2020 11:54 PM, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?

Clifford Heath

I don\'t know how to fix it off hand but the rejection at 10kHz from V1
to V2 kinda sucks:

https://imgur.com/a/w6p7Y37
Click to expand...

Retry: <https://imgur.com/a/1cKijPC>
 
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that has
quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too much
supply noise onto the line and upset the signalling. It doesn\'t matter
how big an output capacitor would be, the linear regulator would
aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For reasons
of supply headroom, I want to combine a gyrator with regulation down to
nominal 5V.

The attached circuit does this ok... but I can\'t work out why it doesn\'t
work better. The Sziklai pair is operating at a gain around 250,000, so
should be multiplying the 10uF capacitance of C3 by something in that
order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?
Click to expand...

Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro
 
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro
Click to expand...

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).
 
On 10/11/2020 12:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that has
quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too much
supply noise onto the line and upset the signalling. It doesn\'t matter
how big an output capacitor would be, the linear regulator would
aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For reasons
of supply headroom, I want to combine a gyrator with regulation down to
nominal 5V.

The attached circuit does this ok... but I can\'t work out why it doesn\'t
work better. The Sziklai pair is operating at a gain around 250,000, so
should be multiplying the 10uF capacitance of C3 by something in that
order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?

Clifford Heath
--- Chop with axe ---
Version 4
SHEET 1 1608 1700
WIRE 704 -80 576 -80
WIRE -480 48 -544 48
WIRE -288 48 -480 48
WIRE -144 48 -288 48
WIRE 0 48 -48 48
WIRE 80 48 0 48
WIRE 208 48 160 48
WIRE 352 48 208 48
WIRE 544 48 352 48
WIRE 576 48 576 -80
WIRE 576 48 544 48
WIRE 608 48 576 48
WIRE -544 144 -544 48
WIRE -96 160 -96 112
WIRE 0 160 0 48
WIRE 704 272 704 -80
WIRE -288 288 -288 48
WIRE -208 288 -288 288
WIRE -48 288 -48 224
WIRE -48 288 -128 288
WIRE 32 288 -48 288
WIRE 208 288 208 48
WIRE 208 288 112 288
WIRE -544 336 -544 224
WIRE 544 336 544 48
WIRE 352 352 352 48
WIRE -48 368 -48 288
WIRE 0 368 -48 368
WIRE 208 368 208 288
WIRE 208 368 64 368
WIRE 704 416 704 336
WIRE -48 432 -48 368
WIRE -48 528 -48 512
WIRE -48 544 -48 528
WIRE -544 624 -544 416
WIRE -48 624 -48 608
WIRE 352 624 352 416
WIRE 544 624 544 416
WIRE 704 624 704 496
FLAG 544 624 0
FLAG 608 48 Vout
FLAG -544 624 0
FLAG -48 624 0
FLAG 704 624 0
FLAG 352 624 0
FLAG -48 288 Vb
FLAG 0 48 Vee
FLAG -480 48 Vline
FLAG -48 528 Vz
SYMBOL res 528 320 R0
SYMATTR InstName R1
SYMATTR Value 47R
SYMBOL voltage 704 400 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -61 129 Left 2
WINDOW 3 -63 102 Left 2
SYMATTR SpiceLine Rser=10
SYMATTR InstName V1
SYMATTR Value PULSE(-2 2 0.001 1u 10u 50u 100u)
SYMBOL res -112 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 470k
SYMBOL cap 0 384 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL zener -32 608 R180
WINDOW 0 47 31 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMBOL res 176 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 3.3R
SYMBOL res 128 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage -544 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 118 Left 2
SYMATTR SpiceLine Rser=5R
SYMATTR InstName V2
SYMATTR Value 14V
SYMBOL cap 688 272 R0
SYMATTR InstName C1
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL cap 336 352 R0
SYMATTR InstName C2
SYMATTR Value 47u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL ind -560 128 R0
SYMATTR InstName L1
SYMATTR Value 22mH
SYMATTR SpiceLine Rser=0.1
SYMBOL npn -96 224 R270
WINDOW 0 -7 4 VRight 2
WINDOW 3 73 6 VRight 2
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL pnp -48 112 M270
WINDOW 0 -7 86 VLeft 2
WINDOW 3 81 94 VLeft 2
SYMATTR InstName Q1
SYMATTR Value 2N5401
SYMBOL res -64 416 R0
SYMATTR InstName R2
SYMATTR Value 47k
TEXT -416 624 Left 2 !.tran 60m
TEXT -232 752 Left 2 ;HomeBus Gyrator/Regulator
TEXT 648 664 Left 2 ;Load variation
TEXT 568 432 Left 2 ;DC load
TEXT -568 672 Left 2 ;HomeBus source
Click to expand...

Increasing R3 as high as you can bear will help of course. Preloading Q2
by adding 1k or 2k resistor across Q1 e-b helps too at high frequencies.
Changing the 2N5401 to 2N4403 results in an instant spice improvement to
20mV.

More radically changing Q1 to a pmos e.g. BSS84 gets you lower.

You could try changing the Sziklai to a single nmos e.g. 2N7002 (zener
and R4 will need changing for Dc reasons) you\'d lose some DC certainty
but AC performance could be good.

I haven\'t tried changing the Sziklai to Darlington or trilington of
using a cascode arrangement but maybe worth a try too.

piglet

Science teaches us to verify.
 
On 10/11/2020 12:34 pm, piglet wrote:
On 10/11/2020 12:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge rectifier,
but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how to
fix it?

Clifford Heath
--- Chop with axe ---
Version 4
SHEET 1 1608 1700
WIRE 704 -80 576 -80
WIRE -480 48 -544 48
WIRE -288 48 -480 48
WIRE -144 48 -288 48
WIRE 0 48 -48 48
WIRE 80 48 0 48
WIRE 208 48 160 48
WIRE 352 48 208 48
WIRE 544 48 352 48
WIRE 576 48 576 -80
WIRE 576 48 544 48
WIRE 608 48 576 48
WIRE -544 144 -544 48
WIRE -96 160 -96 112
WIRE 0 160 0 48
WIRE 704 272 704 -80
WIRE -288 288 -288 48
WIRE -208 288 -288 288
WIRE -48 288 -48 224
WIRE -48 288 -128 288
WIRE 32 288 -48 288
WIRE 208 288 208 48
WIRE 208 288 112 288
WIRE -544 336 -544 224
WIRE 544 336 544 48
WIRE 352 352 352 48
WIRE -48 368 -48 288
WIRE 0 368 -48 368
WIRE 208 368 208 288
WIRE 208 368 64 368
WIRE 704 416 704 336
WIRE -48 432 -48 368
WIRE -48 528 -48 512
WIRE -48 544 -48 528
WIRE -544 624 -544 416
WIRE -48 624 -48 608
WIRE 352 624 352 416
WIRE 544 624 544 416
WIRE 704 624 704 496
FLAG 544 624 0
FLAG 608 48 Vout
FLAG -544 624 0
FLAG -48 624 0
FLAG 704 624 0
FLAG 352 624 0
FLAG -48 288 Vb
FLAG 0 48 Vee
FLAG -480 48 Vline
FLAG -48 528 Vz
SYMBOL res 528 320 R0
SYMATTR InstName R1
SYMATTR Value 47R
SYMBOL voltage 704 400 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -61 129 Left 2
WINDOW 3 -63 102 Left 2
SYMATTR SpiceLine Rser=10
SYMATTR InstName V1
SYMATTR Value PULSE(-2 2 0.001 1u 10u 50u 100u)
SYMBOL res -112 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 470k
SYMBOL cap 0 384 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL zener -32 608 R180
WINDOW 0 47 31 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMBOL res 176 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 3.3R
SYMBOL res 128 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage -544 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 118 Left 2
SYMATTR SpiceLine Rser=5R
SYMATTR InstName V2
SYMATTR Value 14V
SYMBOL cap 688 272 R0
SYMATTR InstName C1
SYMATTR Value 10u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL cap 336 352 R0
SYMATTR InstName C2
SYMATTR Value 47u
SYMATTR SpiceLine Rser=12m Lser=10n Rpar=3e6 Cpar=3e-9
SYMBOL ind -560 128 R0
SYMATTR InstName L1
SYMATTR Value 22mH
SYMATTR SpiceLine Rser=0.1
SYMBOL npn -96 224 R270
WINDOW 0 -7 4 VRight 2
WINDOW 3 73 6 VRight 2
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL pnp -48 112 M270
WINDOW 0 -7 86 VLeft 2
WINDOW 3 81 94 VLeft 2
SYMATTR InstName Q1
SYMATTR Value 2N5401
SYMBOL res -64 416 R0
SYMATTR InstName R2
SYMATTR Value 47k
TEXT -416 624 Left 2 !.tran 60m
TEXT -232 752 Left 2 ;HomeBus Gyrator/Regulator
TEXT 648 664 Left 2 ;Load variation
TEXT 568 432 Left 2 ;DC load
TEXT -568 672 Left 2 ;HomeBus source

Increasing R3 as high as you can bear will help of course. Preloading Q2
by adding 1k or 2k resistor across Q1 e-b helps too at high frequencies.
Changing the 2N5401 to 2N4403 results in an instant spice improvement to
20mV.

More radically changing Q1 to a pmos e.g. BSS84 gets you lower.

You could try changing the Sziklai to a single nmos e.g. 2N7002 (zener
and R4 will need changing for Dc reasons) you\'d lose some DC certainty
but AC performance could be good.

I haven\'t tried changing the Sziklai to Darlington or trilington of
using a cascode arrangement but maybe worth a try too.

piglet

Science teaches us to verify.
Click to expand...

Forgot to add the most obvious - increase C2 !

piglet

Science teaches us to verify.
 
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge
rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).
Click to expand...

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

<https://imgur.com/a/0QFsGKT>
 
On 10/11/2020 4:09 pm, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud. Power
is typically fed through something equivalent to a 22mH inductor,
with a DC resistance around 5 ohms but dynamic impedance more like
200 ohms. It can be connected in either polarity, so the first step
is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT
Click to expand...

Cool! I was thinking of an NPN cascode instead but your PNP looks very
promising. You can omit the 470k R7 and 100k R4 and 47k R2 since the
zener is now biased by 4.7k R6. Then the OPs wanted 5.6V zener should be
just right. It looks like win-win all round.

piglet

Science teaches us to verify.
 
On 11/10/2020 11:26 AM, piglet wrote:
On 10/11/2020 4:09 pm, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud.
Power is typically fed through something equivalent to a 22mH
inductor, with a DC resistance around 5 ohms but dynamic impedance
more like 200 ohms. It can be connected in either polarity, so the
first step is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit
that has quite bursty current consumption but doesn\'t require a
strictly regulated voltage. So a linear regulator is out, or I\'ll
couple too much supply noise onto the line and upset the
signalling. It doesn\'t matter how big an output capacitor would be,
the linear regulator would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT

Cool! I was thinking of an NPN cascode instead but your PNP looks very
promising. You can omit the 470k R7 and 100k R4 and 47k R2 since the
zener is now biased by 4.7k R6. Then the OPs wanted 5.6V zener should be
just right. It looks like win-win all round.

piglet

Science teaches us to verify.
Click to expand...

Yeah. Just strap C3 back to the base of the darlington. Increase C4 to
2.2u, and this reduces Vline ripple to about 500 microvolts P2P.
 
On 11/10/2020 11:36 AM, bitrex wrote:
On 11/10/2020 11:26 AM, piglet wrote:
On 10/11/2020 4:09 pm, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud.
Power is typically fed through something equivalent to a 22mH
inductor, with a DC resistance around 5 ohms but dynamic impedance
more like 200 ohms. It can be connected in either polarity, so the
first step is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit
that has quite bursty current consumption but doesn\'t require a
strictly regulated voltage. So a linear regulator is out, or I\'ll
couple too much supply noise onto the line and upset the
signalling. It doesn\'t matter how big an output capacitor would
be, the linear regulator would aggressively recharge it on usage
spikes.

The classic approach is to use a 22mH inductor, and that would
work fine, but as in telephony, everybody uses gyrators instead.
For reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain
around 250,000, so should be multiplying the 10uF capacitance of
C3 by something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and
how to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of
only two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT

Cool! I was thinking of an NPN cascode instead but your PNP looks very
promising. You can omit the 470k R7 and 100k R4 and 47k R2 since the
zener is now biased by 4.7k R6. Then the OPs wanted 5.6V zener should
be just right. It looks like win-win all round.

piglet

Science teaches us to verify.


Yeah. Just strap C3 back to the base of the darlington. Increase C4 to
2.2u, and this reduces Vline ripple to about 500 microvolts P2P.
Click to expand...

Have to use the sziklai again for 5.6 zener to be right, but performance
looks about the same.
 
On 10/11/2020 16:46, bitrex wrote:
On 11/10/2020 11:36 AM, bitrex wrote:
On 11/10/2020 11:26 AM, piglet wrote:
On 10/11/2020 4:09 pm, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud.
Power is typically fed through something equivalent to a 22mH
inductor, with a DC resistance around 5 ohms but dynamic
impedance more like 200 ohms. It can be connected in either
polarity, so the first step is a bridge rectifier, but I\'ve
ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit
that has quite bursty current consumption but doesn\'t require a
strictly regulated voltage. So a linear regulator is out, or I\'ll
couple too much supply noise onto the line and upset the
signalling. It doesn\'t matter how big an output capacitor would
be, the linear regulator would aggressively recharge it on usage
spikes.

The classic approach is to use a 22mH inductor, and that would
work fine, but as in telephony, everybody uses gyrators instead.
For reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain
around 250,000, so should be multiplying the 10uF capacitance of
C3 by something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and
how to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of
only two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT

Cool! I was thinking of an NPN cascode instead but your PNP looks
very promising. You can omit the 470k R7 and 100k R4 and 47k R2 since
the zener is now biased by 4.7k R6. Then the OPs wanted 5.6V zener
should be just right. It looks like win-win all round.

piglet

Science teaches us to verify.


Yeah. Just strap C3 back to the base of the darlington. Increase C4 to
2.2u, and this reduces Vline ripple to about 500 microvolts P2P.

Have to use the sziklai again for 5.6 zener to be right, but performance
looks about the same.
Click to expand...

Soz, I didn\'t try your Darlington but just hacked the OP Sziklai

piglet
 
On 10/11/2020 16:36, bitrex wrote:
On 11/10/2020 11:26 AM, piglet wrote:
On 10/11/2020 4:09 pm, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud.
Power is typically fed through something equivalent to a 22mH
inductor, with a DC resistance around 5 ohms but dynamic impedance
more like 200 ohms. It can be connected in either polarity, so the
first step is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit
that has quite bursty current consumption but doesn\'t require a
strictly regulated voltage. So a linear regulator is out, or I\'ll
couple too much supply noise onto the line and upset the
signalling. It doesn\'t matter how big an output capacitor would
be, the linear regulator would aggressively recharge it on usage
spikes.

The classic approach is to use a 22mH inductor, and that would
work fine, but as in telephony, everybody uses gyrators instead.
For reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain
around 250,000, so should be multiplying the 10uF capacitance of
C3 by something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and
how to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of
only two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT

Cool! I was thinking of an NPN cascode instead but your PNP looks very
promising. You can omit the 470k R7 and 100k R4 and 47k R2 since the
zener is now biased by 4.7k R6. Then the OPs wanted 5.6V zener should
be just right. It looks like win-win all round.

piglet

Science teaches us to verify.


Yeah. Just strap C3 back to the base of the darlington. Increase C4 to
2.2u, and this reduces Vline ripple to about 500 microvolts P2P.
Click to expand...

A big C4 might stress the base junction at power up?

piglet
 
On 11/11/20 3:09 am, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud. Power
is typically fed through something equivalent to a 22mH inductor,
with a DC resistance around 5 ohms but dynamic impedance more like
200 ohms. It can be connected in either polarity, so the first step
is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT
Click to expand...

Cool stuff, thanks. I\'ll have to check it after adding the signalling
(from a 3rd party or local Tx) that might be happening on Vline though.
The PULSE source shown simulated varying load, but VLine also has
alternating +ve and -ve 2V pulses on it and we don\'t want that to send
the gyrator crazy.

Clifford Heath
 
On 10/11/20 11:55 pm, piglet wrote:
On 10/11/2020 12:34 pm, piglet wrote:
On 10/11/2020 12:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device feeding
power at nominally 14V, with superimposed RS232-ish signalling of 2V
alternate-space-inversion pulses at 9600baud. Power is typically fed
through something equivalent to a 22mH inductor, with a DC resistance
around 5 ohms but dynamic impedance more like 200 ohms. It can be
connected in either polarity, so the first step is a bridge
rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?

Clifford Heath
--- Chop with axe ---
Click to expand...

[clip]

Increasing R3 as high as you can bear will help of course. Preloading
Q2 by adding 1k or 2k resistor across Q1 e-b helps too at high
frequencies. Changing the 2N5401 to 2N4403 results in an instant spice
improvement to 20mV.

More radically changing Q1 to a pmos e.g. BSS84 gets you lower.

You could try changing the Sziklai to a single nmos e.g. 2N7002 (zener
and R4 will need changing for Dc reasons) you\'d lose some DC certainty
but AC performance could be good.

I haven\'t tried changing the Sziklai to Darlington or trilington of
using a cascode arrangement but maybe worth a try too.

piglet

Science teaches us to verify.

Forgot to add the most obvious - increase C2 !
Click to expand...

Oh, yeah - I was intending to use 680uF but reduced it to see how the
underlying circuit works. Didn\'t want to simply mask the gyrator effect
with a too-large output cap. It actually looks quite on with 680uF.

Thanks for all your ideas.

Clifford Heath
 
On 10/11/20 11:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system,...

Can anyone figure out why this noise is getting into Vline,
Click to expand...

I still don\'t really have an answer to this, BTW - though folk suggested
various ways to fix it. The effect in the original circuit seems
disproportionate.

Another thought occurred, but I don\'t know where to get a model I can
rely on to simulate it:

Why not use a three-terminal regulator as the active element in a
gyrator? Just stand the earthy side on a resistor, biassed with a
resistor from the input to swamp quiescent currents, and feed a
capacitor back to that point from the output.

Would you expect that to work, or oscillate?
Where can I find a solid Spice model for e.g. a 7805?

Clifford Heath
 
On 11/11/20 3:09 am, bitrex wrote:
On 11/10/2020 4:14 AM, Clifford Heath wrote:
On 10/11/20 4:06 pm, bitrex wrote:
On 11/9/2020 7:32 PM, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system, which is
variously known by different manufacturer\'s names:

Daiken: P1/P2 or F1/F2
Mitsubishi: M-Net
Toshiba: TCC-Link
Hitachi: H-link
Panasonic/Sanyo: SIII-Net.
Other manufacturers use it too, e.g. Rinnai

See Chapter 4 of the EchoNet standard here:
https://echonet.jp/wp/wp-content/uploads/pdf/General/Standard/Echonet/Version_2_11_en/spec_v211e_3.pdf


Anyhow, it\'s a single pair multi-drop network with one device
feeding power at nominally 14V, with superimposed RS232-ish
signalling of 2V alternate-space-inversion pulses at 9600baud. Power
is typically fed through something equivalent to a 22mH inductor,
with a DC resistance around 5 ohms but dynamic impedance more like
200 ohms. It can be connected in either polarity, so the first step
is a bridge rectifier, but I\'ve ignored that.

Out of this supply, I want to draw up to 100mA for a 5V circuit that
has quite bursty current consumption but doesn\'t require a strictly
regulated voltage. So a linear regulator is out, or I\'ll couple too
much supply noise onto the line and upset the signalling. It doesn\'t
matter how big an output capacitor would be, the linear regulator
would aggressively recharge it on usage spikes.

The classic approach is to use a 22mH inductor, and that would work
fine, but as in telephony, everybody uses gyrators instead. For
reasons of supply headroom, I want to combine a gyrator with
regulation down to nominal 5V.

The attached circuit does this ok... but I can\'t work out why it
doesn\'t work better. The Sziklai pair is operating at a gain around
250,000, so should be multiplying the 10uF capacitance of C3 by
something in that order.

I still see about 30mV of noise being injected into the line, and
nothing I\'ve tweaked seems to reduce that by much.

Can anyone figure out why this noise is getting into Vline, and how
to fix it?


Also why u use a 6.2 volt Zener as a reference? Use a TL431 or
something. Time to get into the 1980s, bro

I used what was available quickly in LTSpice.

For prototype production, I\'ll use the 5v6 zener which is one of only
two zeners on JLCPCB\'s \"Basic\" list (no extra reel-loading cost).

Try the cascode my dude, it looks better (may have to increase zener
voltage/adjust some values to get the output voltage you want):

https://imgur.com/a/0QFsGKT
Click to expand...

Hmmm, Q1/C4 mean that when there\'s any signalling on Vline, the gyrator
only draw power from the +ve pulses, and Q1 turns off at other times.
That\'s not the desired effect. Perils of a partial simulation.

Clifford Heath.
 
Clifford Heath <no.spam@please.net> wrote:

On 10/11/20 11:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system,...

Can anyone figure out why this noise is getting into Vline,

I still don\'t really have an answer to this, BTW - though folk suggested
various ways to fix it. The effect in the original circuit seems
disproportionate.

Another thought occurred, but I don\'t know where to get a model I can
rely on to simulate it:

Why not use a three-terminal regulator as the active element in a
gyrator? Just stand the earthy side on a resistor, biassed with a
resistor from the input to swamp quiescent currents, and feed a
capacitor back to that point from the output.

Would you expect that to work, or oscillate?
Where can I find a solid Spice model for e.g. a 7805?

Clifford Heath
Click to expand...

Lots of examples in google. Try LM7805

--
Science teaches us to trust. - sw
 
Steve Wilson <spam@me.com> wrote:

Clifford Heath <no.spam@please.net> wrote:

On 10/11/20 11:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system,...

Can anyone figure out why this noise is getting into Vline,

I still don\'t really have an answer to this, BTW - though folk
suggested various ways to fix it. The effect in the original circuit
seems disproportionate.

Another thought occurred, but I don\'t know where to get a model I can
rely on to simulate it:

Why not use a three-terminal regulator as the active element in a
gyrator? Just stand the earthy side on a resistor, biassed with a
resistor from the input to swamp quiescent currents, and feed a
capacitor back to that point from the output.

Would you expect that to work, or oscillate?
Where can I find a solid Spice model for e.g. a 7805?

Clifford Heath

Lots of examples in google. Try LM7805
Click to expand...

Better:

https://groups.io/g/LTspice/search?q=lm7805



--
Science teaches us to trust. - sw
 
On 11/11/20 1:07 pm, Steve Wilson wrote:
Steve Wilson <spam@me.com> wrote:

Clifford Heath <no.spam@please.net> wrote:

On 10/11/20 11:32 am, Clifford Heath wrote:
I\'m designing an interface to an HBS (HomeBus) system,...

Can anyone figure out why this noise is getting into Vline,

I still don\'t really have an answer to this, BTW - though folk
suggested various ways to fix it. The effect in the original circuit
seems disproportionate.

Another thought occurred, but I don\'t know where to get a model I can
rely on to simulate it:

Why not use a three-terminal regulator as the active element in a
gyrator? Just stand the earthy side on a resistor, biassed with a
resistor from the input to swamp quiescent currents, and feed a
capacitor back to that point from the output.

Would you expect that to work, or oscillate?
Where can I find a solid Spice model for e.g. a 7805?

Clifford Heath

Lots of examples in google. Try LM7805

Better:

https://groups.io/g/LTspice/search?q=lm7805
Click to expand...

You reckon that some random search that turns up a model for a device
meant to work as a regulator will work ok for simulating it in a
completely different mode of operation? Ok, maybe it will... but you
have more trust than I do.

CH
 
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