Guidance needed in developing a Verification model.

Guest
Hi all,
I am a newcomer in the field of ASIC verification and to Verilog as
well. I have to develop a verification model of National's 16550D UART
(the design is already existing). I have seen the datasheet of 16550D
and it contains around 12 registers (some read-only, some write-only
and the remaining both read-write).

I have practically never worked at developing verification models of
any real device before and so, the sheer volume of combinations of
parameters to be considered in the 16550D is unnerving me, though it is
just a UART (I can now very well imagine the verification process of
much more complex devices).

Just to make a start, I am not able to make a blueprint of the
methodology that should be followed to execute a task like this.

If someone could tell me a step by step procedure to carry this out (or
point me to any relevant links), I'd be really grateful.

Best regards,
Amit.
 
Two books:
1. "Verification Plans: the Five-Day Verification Strategy for Modern
Hardware Verification Languages" by Peet James
2. "Writing Testbenches using SystemVerilog" by Janick Bergeron.

-cb
 
Avoid directed tests.
See
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1222
for a discussion on tests.
You may want to consider SystemVerilog with constrained-random tests.
Also, take a look at VMM for methodology.

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* Training for VMM, SVA and PSL
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
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* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
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