A
Avnish Mishra
Guest
Hi All,
My name is Avnish. I am doing course in VLSI Front End
Designing.I have completed Verilog. So just want a suggestion and
Guidance on the project related to verilog. So that I can implement
the basics i learned during the course. Looking forward for your
response.
Thank you
Avnish
My name is Avnish. I am doing course in VLSI Front End
Designing.I have completed Verilog. So just want a suggestion and
Guidance on the project related to verilog. So that I can implement
the basics i learned during the course. Looking forward for your
response.
Thank you
Avnish