Guess: what is the largest number of state machines in a cur

W

Weng Tianxiang

Guest
Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng
 
On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng
Click to expand...

I am afraid as it stands your question does not make any sense.

These state machines:
1. How many states does each has?
2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work
questionable. Maybe you could live with a smaller number of FSMs. I
just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias
 
On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng

I am afraid as it stands your question does not make any sense.

These state machines:
1. How many states does each has?
2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work
questionable. Maybe you could live with a smaller number of FSMs. I
just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias
Click to expand...
Hi NK,
The guess is about what the largest number of state machine a current
chip may contain is.

It doesn't ask how many states each state machine has or what coding
method is used.

Just guess the largest number of state machine in a current chip
design.

It is not an easy guess, because your experiences may fall short of
imagination.

Why I listed 27 state machines is I used to make a wrong guessing
about the number, only based on my experiences with digital designs. I
guess most of experienced engineers may have the same experiences as I
had.

Weng
 
On Sep 17, 1:55 am, Weng Tianxiang <wtx...@gmail.com> wrote:
On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:



On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng

I am afraid as it stands your question does not make any sense.

These state machines:
1. How many states does each has?
2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work
questionable. Maybe you could live with a smaller number of FSMs. I
just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias

Hi NK,
The guess is about what the largest number of state machine a current
chip may contain is.

It doesn't ask how many states each state machine has or what coding
method is used.

Just guess the largest number of state machine in a current chip
design.

It is not an easy guess, because your experiences may fall short of
imagination.

Why I listed 27 state machines is I used to make a wrong guessing
about the number, only based on my experiences with digital designs. I
guess most of experienced engineers may have the same experiences as I
had.

Weng
Click to expand...
The most state machines any design can have is the same as the number
of registers available on the design. Each register could be counted
as a 2 state FSM. so in todays FPGAs, there are is a maximum of
somewhere in the hundreds of thousands of FSMs.
 
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1189988802.612765.289620@50g2000hsm.googlegroups.com...
Weng
Click to expand...
IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;

HTH., Syms. ;-)

p.s. Sorry, couldn't resist it!

p.p.s. I guess one. You can view the whole FPGA as one big state machine. Do
I win Ł5?
 
Hi,
I don't say how many state machines a design CAN or MAY generate, but
I say GUESS what the largest number of state machines a real design
ACTUALLY HAS GENERATED and those state machines are critical, not
trivial in design functions.

The problem core is how you know other people's design internal
affairs?

You may not have a chance to generate so many state machines and you
may not have the knowledge about why there are so many state
machines.

I guess less than 27 engineers in the world who have a chance to do
the designs and have the experiences.

All who have responded to the post so far seem to be no knowledge
about it and just missed the target.

Weng
 
Weng Tianxiang wrote:
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.
Click to expand...
As others have said, how do you define a state machine? Is an SRAM bit a state
machine? They fit quite a few of them onto a chip these days...

(followups set to remove crosspost)

--
Philip Potter pgp <at> doc.ic.ac.uk
 
Weng Tianxiang wrote:

I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...
Click to expand...
This is not an easy question.

I could say that every flip-flop is a state machine, in which case the
number is very large. I could say that the entire system is a state
machine, in which case the answer is one.

We partition systems when we design them, and design separate state
machines. Others may look at the system differently, and find
a different count.

-- glen
 
Weng Tianxiang wrote:

I have to expand the guess to include Verilog group people, because
VHDL people may have no chance to do the designs.
Click to expand...
Please clarify.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
Weng Tianxiang wrote:

I guess there are less than 27 engineers in the world who have the
experiences to do the designs.
Click to expand...
Must be a strange world you live in...

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
On Sep 17, 2:46 pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
Weng Tianxiang wrote:
I guess there are less than 27 engineers in the world who have the
experiences to do the designs.

Must be a strange world you live in...

And of course the implication is there is really only 26 OTHER
Click to expand...
engineers.

Shannon
 
Weng Tianxiang wrote:
Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng
Click to expand...
So are you talking about a Silicon Ceiling, or a Software Ceiling ?

-jg
 
Symon wrote:

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1189988802.612765.289620@50g2000hsm.googlegroups.com...

Weng



IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;

HTH., Syms. ;-)

p.s. Sorry, couldn't resist it!
Click to expand...
:)

Whoa - hang on there, Syms !!!!

What's this ANDIF, BUTIF ?!?!

You can't use that until there has been a long discussion first ?! ;)

( I like the sound of the BUTIF, you might be onto something there... )

-jg
 
IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;
....

What's this ANDIF, BUTIF ?!?!
Click to expand...
And I was hoping for an ORELSE :)
 
I gave my guess. Why haven't you responded? You told me you would
tell me the answer after I guessed. Now tell me.

Shannon
 
IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;

HTH., Syms. ;-)

p.s. Sorry, couldn't resist it!

p.p.s. I guess one. You can view the whole FPGA as one big state machine.
Do I win Ł5?
Click to expand...
ROFL, how could I have missed this posting for 3 days... LOL

Thomas
 
On Sun, 16 Sep 2007 17:26:42 -0700, Weng Tianxiang <wtxwtx@gmail.com>
wrote:

Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng
Click to expand...
According to a show I just saw on the History Channel, during the last
days of World War II, Adolph Hitler paced up and down the halls of his
bunker, trying to determine the number of state machines you could fit
into a 12AU7.

By the power vested in me by the First Corollary of Godwin's Law, I
declare this thread officially over.

No need to thank me,
Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com
 
Jim Lewis wrote:
IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;
...

What's this ANDIF, BUTIF ?!?!


And I was hoping for an ORELSE :)
Click to expand...
Coming soon to a thread near you: ELSEMAYBEIF, ELSECONFUSEDIF,
ELSERANDOMIF, etc.

I wonder if Weng will ever quit creating and feeding these very much
pointless threads. Maybe he's just a bad comedian.
 
On Sep 19, 9:54 am, Shannon <sgo...@sbcglobal.net> wrote:
I gave my guess. Why haven't you responded? You told me you would
tell me the answer after I guessed. Now tell me.

Shannon
Click to expand...
Hi Sannon,
1. It is L2 cache that uses a lot of state machines;
http://en.wikipedia.org/wiki/Cache_coherence

2. IBM/Intel uses MESI protocol (Modified, Eclusive, Shared and
Invalid);
http://en.wikipedia.org/wiki/MESI_protocol

3. Please visit Intel product website to get the latest news:
http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf

4. "with up to 8 MB of L2 cache per processor" and 4 cores.
It means 4*8MB = 32MB L2 cache;

5. Each 32Bytes is a cache line;

6. 32MB/32 = 1M cache lines and 1M state machines.

The final answer is:
There is at least 1M state machines in Intel chip.

a. It is available to every users in the topics groups;
b. They are written in Verilog, not in VHDL;
c. FPGA has never had a design using L2 cache.

Any more questions?

Weng
 
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