GSR from glbl library (Xilinx ISE)

[thomasc]

Hi all,

I'm a newbie in FPGA and I got stuck while trying to simulate
post-synthesis simulation models that were generated by Xilinx ISE 6.3.

I declared a reset signal in my design and testbench. When I tried to
simulate the post-synthesis models, my design didn't seem to be reacting
to the reset signal I declared. Besides, while synthsizing, Xilnx ISE
automatically imported a signal called GSR(Global Set Reset?) from glbl
library.

1) I was wondering if I needed to use this GSR signal as reset of my
design.

2) If so, should I make my design sensitive to negedge GSR or negaive GSR?


3) I haven't been able to find out how to use GSR in my design. I tried to
istanciate glbl by writng something like "glbl GB ();". But it didn't work.
is there a particular way to use GSR in my design?

Thanks much in advance!

 

[Jason Zheng]

thomasc wrote:

Hi all,

I'm a newbie in FPGA and I got stuck while trying to simulate
post-synthesis simulation models that were generated by Xilinx ISE 6.3.

I declared a reset signal in my design and testbench. When I tried to
simulate the post-synthesis models, my design didn't seem to be reacting
to the reset signal I declared. Besides, while synthsizing, Xilnx ISE
automatically imported a signal called GSR(Global Set Reset?) from glbl
library.

1) I was wondering if I needed to use this GSR signal as reset of my
design.

I never have to use it, though I'm not sure what it does. I think you
should trace the reset signals from your FF and see what's driving it.

cheers,

jz

 

[B. Joshua Rosen]

On Mon, 13 Jun 2005 21:17:15 -0400, thomasc wrote:

Hi all,

I'm a newbie in FPGA and I got stuck while trying to simulate
post-synthesis simulation models that were generated by Xilinx ISE 6.3.

I declared a reset signal in my design and testbench. When I tried to
simulate the post-synthesis models, my design didn't seem to be reacting
to the reset signal I declared. Besides, while synthsizing, Xilnx ISE
automatically imported a signal called GSR(Global Set Reset?) from glbl
library.

1) I was wondering if I needed to use this GSR signal as reset of my
design.

2) If so, should I make my design sensitive to negedge GSR or negaive GSR?


3) I haven't been able to find out how to use GSR in my design. I tried to
istanciate glbl by writng something like "glbl GB ();". But it didn't work.
is there a particular way to use GSR in my design?

Thanks much in advance!

You need to instantiate a glbl module in your testbench so that the GSR
signal is defined. The STARTUP model connects your reset to GSR.


//-- Component Instance glbl
glbl glbl
(

);

module glbl ();

wire GR;
wire GSR;
wire GTS;
wire PRLD;

endmodule

 

[Berty]

When running post synthesis or P&R you need to call the glbl.v however
I for one never had to do anything with the GSR.

My reset signal come from a IO and this is the only signal I have to
control in my test bench.

Have Fun.

 

[Berty]

One thing does come to mind how does your glbl.v file look like.

This is the one I now have and as you can see the GSR is already taken
care of in this module.

`timescale 1 ps / 1 ps

module glbl ();

parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;

wire GSR;
wire GTS;
wire PRLD;

reg GSR_int;
reg GTS_int;
reg PRLD_int;

assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;

initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end

initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end

endmodule

Have fun.

 

[Berty]

With your glbl.v file you will most likely experience problem running
post P&R verification since the netlist ISE spit not only "call"
for glbl signals like

wire GSR = glbl.GSR;
wire GTS = glbl.GTS;

but there is also reference to those signal like

X_BUF \abc/tmp/FFY/RSTOR (
.I(GSR),
.O(\abc/tmp/FFY/RST )

which later is used to reset a X_FF.

And so it is more than likely that your design will not be able to
simulate properly.

Have Fun