Good Verilog Reference Book

[Russell Fredrickson]

Hi all,

I have 3-4 years of Verilog experience under my belt as well as some
advanced verilog training (Cliff Cummings course), but I lack a good Verilog
reference book that includes good explanations of the Verilog 2001 features.
So I'm looking for suggestions on a good Verilog book that has all or most
of the following characterictics:

-- Assumes the reader is somewhat proficient at digital design and famliar
with basic programming concepts.
-- Makes a good reference for all the features of Verilog (including Verilog
2001 constructs) -- both synthesizable and non-synthesizable constructs
(ideally the book would identify which constructs are synthesizable and
which are not).
-- Gives good explanation of the various "gotchas" associated with Verilog
RTL coding (i.e. blocking vs. non-blocking statements, accidental latch
inference, etc.).

Thanks,
Russell

 

[Robert Sefton]

Russell -

Buy the LRM if you don't already have it (although it took the IEEE about
six months to send me my copy), and download some good papers, like those
at:

http://www.sunburst-design.com/papers/

http://www.edacafe.com/

Lots of good free information out there. Also consider Janick Bergeron's
book ("Writing Testbenches") and web site:

http://verificationguild.com/

Robert

"Russell Fredrickson" <russell_fredrickson@hp.com> wrote in message
news:cgdl65$nbh$1@news.vcd.hp.com...

Hi all,

I have 3-4 years of Verilog experience under my belt as well as some
advanced verilog training (Cliff Cummings course), but I lack a good
Verilog
reference book that includes good explanations of the Verilog 2001
features.
So I'm looking for suggestions on a good Verilog book that has all or most
of the following characterictics:

-- Assumes the reader is somewhat proficient at digital design and famliar
with basic programming concepts.
-- Makes a good reference for all the features of Verilog (including
Verilog
2001 constructs) -- both synthesizable and non-synthesizable constructs
(ideally the book would identify which constructs are synthesizable and
which are not).
-- Gives good explanation of the various "gotchas" associated with Verilog
RTL coding (i.e. blocking vs. non-blocking statements, accidental latch
inference, etc.).

Thanks,
Russell