P
peter dudley
Guest
Hello All,
It has been many years since I used the Synopsys Design Constraint (SDC) language to apply timing constraints to a logic design. Right now I am working on a preexisting Altera Cyclone 4 FPGA design and I believe that the I/O constraints are not complete. Unfortunately, my first attempts to constrain I/O on the part result in Altera timing reports that are incomprehensible to me. Some of the clocking schemes in this part are very complicated. I think I need to go back to school and really understand SDC.
Can anyone recommend a good "Theory and Practice" document for SDC timing constraints?
Thank you for any advice.
Pete Dudley
It has been many years since I used the Synopsys Design Constraint (SDC) language to apply timing constraints to a logic design. Right now I am working on a preexisting Altera Cyclone 4 FPGA design and I believe that the I/O constraints are not complete. Unfortunately, my first attempts to constrain I/O on the part result in Altera timing reports that are incomprehensible to me. Some of the clocking schemes in this part are very complicated. I think I need to go back to school and really understand SDC.
Can anyone recommend a good "Theory and Practice" document for SDC timing constraints?
Thank you for any advice.
Pete Dudley