Gold code generator

[Dimcliff]

Hi,
I'm a newbie in vhdl programming. But I have to make a gold code
generator in a xillinx fpga device.
My problem is that the application note from xillinx does not work
properly at the test bench. If anyone could help me with an other code,
or something else i would appreciate it.
You know i'm desperate right now because i need to finish my university
school with this project and i can't find the problem.

 

[Mike Treseler]

Dimcliff wrote:

I'm a newbie in vhdl programming. But I have to make a gold code
generator in a xillinx fpga device.

That doesn't seem too difficult,
since the code is already written for you.
See pg 8 in
http://www.xilinx.com/bvdocs/appnotes/xapp217.pdf

Let's have a look at the unzipped files:

VSIM 7> vcom vhd_suba.vhd vhd_subb.vhd vhd_top.vhd
vcom vhd_suba.vhd vhd_subb.vhd vhd_top.vhd
# Model Technology ModelSim ALTERA vcom 6.0e Compiler 2005.06 Jun 18 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity lfsr_a
# -- Compiling architecture lfsr_a_arch of lfsr_a
# -- Compiling entity lfsr_b
# -- Compiling architecture lfsr_b_arch of lfsr_b
# -- Compiling entity gold_code
# -- Compiling architecture gold_code_arch of gold_code
VSIM 8> vsim -c gold_code
vsim -c gold_code
# vsim -c gold_code
# Loading c:\Modeltech_ae\win32aloem/../win32aloem/convert_hex2ver.dll
# Loading c:\Modeltech_ae\win32aloem/../std.standard
# Loading c:\Modeltech_ae\win32aloem/../ieee.std_logic_1164(body)
# Loading work.gold_code(gold_code_arch)
# Loading work.lfsr_a(lfsr_a_arch)
# Loading work.lfsr_b(lfsr_b_arch)

The code compiles and elaborates ok.
Note that the top entity is named gold_code, which does not match the
file name. For synthesis, all you need it to
enter the file list with vhd_top.vhd on top and push a button.

My problem is that the application note from xillinx does not work
properly at the test bench.

See page 9 of the pdf. There is no testbench unless you wrote one.

"The code was simulated on MTI's Modelsim simulator using the TCL
interface, therefore, no testbench was used. On a simulator supporting
stimulus using HDL code only, create the testbench (HDL) file to verify
functionality."


-- Mike Treseler

 

[Mark McDougall]

Mike Treseler wrote:

See page 9 of the pdf. There is no testbench unless you wrote one.

Sounds like he's fishing for a completed assignment...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Dimcliff]

Ο/Η Mark McDougall έγραψε:

Mike Treseler wrote:

Sounds like he's fishing for a completed assignment...

Thanks for your help. I'm using xillinx ise8.1i (webpack).the compile
section is ok, but the synthesis show me 13 warnings.Moreover the
waveform source does not give me the results i expect. in that
behavioral mode i have two erros too. Any idea i don't know what to do
but i have to do something.

 

[D Stanford]

Thanks for your help. I'm using xillinx ise8.1i (webpack).the compile
section is ok, but the synthesis show me 13 warnings.

Warnings aren't the same as errors. Sometimes warnings are acceptable.
Unfortunately, you'll have to understand the code to know if the
warning is acceptable or not.

Moreover the
waveform source does not give me the results i expect. in that
behavioral mode i have two erros too. Any idea i don't know what to do
but i have to do something.

Either your expectations are wrong, or the wave is wrong. You'll have
to figure out which. If it's the wave, you'll have to modifiy the VHDL
to function to your expectations.