Global Variables

[Tricky]

Why not combine it all into 1 process?

process(clk, reset)
if reset = '1' then
-- do some reset
elsif rising_edge(clk) then
--do something
elsif falling_edge(clk) then
--do something else
end if;
end process;

But that may be unsynthesizable.

How about doubling the clock speed through a PLL/DCM and just using
the doubled clock to do things in the right order?

 

[Ralf Hildebrandt]

raullim7@hotmail.com schrieb:

because this counter counts from 0-99 and at each count, takes in a
sample value from my circuit. so in the two processes, there will be a
total of 200 samples. however, i need to change my code so that
process1 samples will intersect with process2 samples. for example,
process1 counter=0 takes in a sample by the name one, then process2
counter=0 takes in a sample by the name two, and then process1
counter=1 takes in sample by the name three..etc. i need to arrange
the samples by one, two, three, four, etc..

I am not sure if I understand it right, but what about:

process(reset_n,clk)
if (reset_n='0') then
-- do some reset
elsif rising_edge(clk) then
-- sample M values to sample_vector_r
end if;
end process;

process(reset_n,clk)
if (reset_n='0') then
-- do some reset
elsif falling_edge(clk) then
-- sample M values to sample_vector_f
end if;
end process;

process(sample_vector_r,sample_vector_f)
begin
for N in sample_vector_r'range loop
combined_sample_vector(2*N) <=sample_vector_r(N);
combined_sample_vector(2*N+1)<=sample_vector_f(N);
end loop;
-- combined_sample_vector is twice as long as sample_vector_r
end process;


No interaction between the two processes is necessary - except the same
start condition / reset and the same number of samples.

Ralf

 

[Mike Treseler]

raullim7@hotmail.com wrote:

i need to arrange
the samples by one, two, three, four, etc.. because at the moment, it
will be something like, one,three,five...,two,four,six.. it will only
starts to gather samples from process2 when process1 ends. or can i do
this intersecting in another way? pls advise.. thanks a million!!

Anything is possible, but you have to
write some code and test it on a simulator
to converge on a solution.

-- Mike Treseler

 

On Nov 5, 8:27 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:

raull...@hotmail.com> wrote in message

news:1194243809.323114.18330@e34g2000pro.googlegroups.com...

i am having two PROCESS to take advantage of dual-edge behavior of
the
clock pulse. one process takes care of the rising edge while the
other
process takes care of the falling edge. For the two processes, they
are basically doing exactly the same thing just that one does it
during rising and the other does it during falling..

So they are doing the same thing at different times....that's not the same
as 'doing the same thing'.

i have a problem
here, bcos i have two sets of variables that does the same thing, i
would to ask how do i change it to global variables..

Don't. They are not the same thing (despite what you seem to think).

both countera/b and check1/2 are exactly the same thing but they are
being declared in the process loop. may i know how do i write the
code
to change it to a shared variable that can be used in both process 1
and 2, that means i only have two variables in counter and check
rather than the four that i am having now.. pls help. thanks

Are you being charged for each variable you use? If not, then relax. Get
functionality correct and move on.

KJ

because this counter counts from 0-99 and at each count, takes in a
sample value from my circuit. so in the two processes, there will be a
total of 200 samples. however, i need to change my code so that
process1 samples will intersect with process2 samples. for example,
process1 counter=0 takes in a sample by the name one, then process2
counter=0 takes in a sample by the name two, and then process1
counter=1 takes in sample by the name three..etc. i need to arrange
the samples by one, two, three, four, etc.. because at the moment, it
will be something like, one,three,five...,two,four,six.. it will only
starts to gather samples from process2 when process1 ends. or can i do
this intersecting in another way? pls advise.. thanks a million!!

 

[KJ]

<raullim7@hotmail.com> wrote in message
news:1194243809.323114.18330@e34g2000pro.googlegroups.com...

i am having two PROCESS to take advantage of dual-edge behavior of
the
clock pulse. one process takes care of the rising edge while the
other
process takes care of the falling edge. For the two processes, they
are basically doing exactly the same thing just that one does it
during rising and the other does it during falling..

So they are doing the same thing at different times....that's not the same
as 'doing the same thing'.

i have a problem
here, bcos i have two sets of variables that does the same thing, i
would to ask how do i change it to global variables..

Don't. They are not the same thing (despite what you seem to think).

both countera/b and check1/2 are exactly the same thing but they are
being declared in the process loop. may i know how do i write the
code
to change it to a shared variable that can be used in both process 1
and 2, that means i only have two variables in counter and check
rather than the four that i am having now.. pls help. thanks

Are you being charged for each variable you use? If not, then relax. Get

functionality correct and move on.

KJ

 

i am having two PROCESS to take advantage of dual-edge behavior of
the
clock pulse. one process takes care of the rising edge while the
other
process takes care of the falling edge. For the two processes, they
are basically doing exactly the same thing just that one does it
during rising and the other does it during falling.. i have a problem
here, bcos i have two sets of variables that does the same thing, i
would to ask how do i change it to global variables..

example


PROCESS1
variable countera;
variable check1;


PROCESS2
variable counterb;
variable check2;


both countera/b and check1/2 are exactly the same thing but they are
being declared in the process loop. may i know how do i write the
code
to change it to a shared variable that can be used in both process 1
and 2, that means i only have two variables in counter and check
rather than the four that i am having now.. pls help. thanks

 

i did something like this..

entity change is

..
..
end change;

architecture only of change is
shared variable counter: INTEGER RANGE 0 TO 99:= 0;

begin
PROCESS1
END PROCESS1

PROCESS2 <=== ERROR here (Multi-source on Integers in Concurrent
Assignment.)
END PROCESS2

end only

pls help.. thanks

 

[Jim Lewis]

Why not combine it all into 1 process?

process(clk, reset)
if reset = '1' then
-- do some reset
elsif rising_edge(clk) then
--do something
elsif falling_edge(clk) then
--do something else
end if;
end process;

But that may be unsynthesizable.

How about doubling the clock speed through a PLL/DCM and just using
the doubled clock to do things in the right order?

This is the coding style recommended by
1076.6-2004, the current IEEE VHDL RTL Coding Styles.

If your vendor does not implement this, then kick
them (figuratively - submit a bug report against it).

Jim

 

[Andy]

On Nov 17, 7:37 pm, Jim Lewis <j...@synthworks.com> wrote:

Why not combine it all into 1 process?

process(clk, reset)
if reset = '1' then
-- do some reset
elsif rising_edge(clk) then
--do something
elsif falling_edge(clk) then
--do something else
end if;
end process;

But that may be unsynthesizable.

How about doubling the clock speed through a PLL/DCM and just using
the doubled clock to do things in the right order?

This is the coding style recommended by
1076.6-2004, the current IEEE VHDL RTL Coding Styles.

If your vendor does not implement this, then kick
them (figuratively - submit a bug report against it).

Jim

IINM, 1076.6 assumes the target architecture has double edged register
resources (some FPGAs do, but only in the IO). I have requested that
Synplicity implement the above single process structure using the
familiar 2 flops & 3 XOR gates per bit, which would allow
implementation in any part (IO or fabric) of any FPGA, but they have
not accepted it yet. If they can do TMR, they should certainly be able
to do this.

Synplicity does accept double edged (or any two clocks/edges)
processes as long as the same object is not updated on both edges/
clocks. So does Precision and (I believe) Quartus. Xilinx did not, the
last time I checked.

Andy

 

[Jim Lewis]

Andy

IINM, 1076.6 assumes the target architecture has double edged register
resources (some FPGAs do, but only in the IO). I have requested that
Synplicity implement the above single process structure using the
familiar 2 flops & 3 XOR gates per bit, which would allow
implementation in any part (IO or fabric) of any FPGA, but they have
not accepted it yet.

This was the intent of the working group.

Jim

 

[Andy]

On Nov 19, 11:04 am, Jim Lewis <j...@synthworks.com> wrote:

Andy

IINM, 1076.6 assumes the target architecture has double edged register
resources (some FPGAs do, but only in the IO). I have requested that
Synplicity implement the above single process structure using the
familiar 2 flops & 3 XOR gates per bit, which would allow
implementation in any part (IO or fabric) of any FPGA, but they have
not accepted it yet.

This was the intent of the working group.

Jim

Great! I did not realize that. It would be important not to focus on
the exact implementation of the dual flop circuit, since there are
other forms (XNOR comes to mind), and other optimizations that could
be made on a larger scale (i.e. instead of having one counter with
every bit thusly implemented, it could use two counters with cross-
coupled inputs, and the just the output implemented as above.

Andy