global variables in Verilog

T

thomasc

Guest
I want to find out if it is possible to use global variables in verilog
that are accessible from all the modules in a project(like in C) and if
so, how I can do it. Can anyone please explain using global variables in
Verilog?
Thanks much in advance!
 
declare parameters in a seperate file and then use 'include <filename>
in all other files.
 
thomasc wrote:
I want to find out if it is possible to use global variables in verilog
that are accessible from all the modules in a project(like in C) and if
so, how I can do it. Can anyone please explain using global variables in
Verilog?
Thanks much in advance!

In a sense all variables in verilog are globally accessible by means of
Click to expand...
hierarchical referencing. Hence you can conveniently declare all the
variables that you would like to consider "global" in your top-level
module, e.g. top.v. Then you can access them by top.a, top.b, etc.

-jz
 
I hope this question is in regarding to simulation and modeling only.
Because for synthesis, global variable doesn't make sense.

Anyway in verilog, there is no sense of global variable as compared to
C. But you can have defines for some constant values (which are not
variable :).

Parameters and other data types "has to" be declared inside a <module>.
And these can behave as "global" for tasks declared inside the
<module>. But it is not same as C.
 
MysticSage wrote:
I hope this question is in regarding to simulation and modeling only.
Because for synthesis, global variable doesn't make sense.

Anyway in verilog, there is no sense of global variable as compared to
C. But you can have defines for some constant values (which are not
variable :).

Parameters and other data types "has to" be declared inside a <module>.
And these can behave as "global" for tasks declared inside the
module>. But it is not same as C.

That's true, my comment reguarding putting your global variables in the
Click to expand...
top-level really only applies to test benches. In real RTL design you
should not reference signals across modular boundary, use an
input/output port instead.

jz
 
Thanks for the reply.

Even if I imagine a hardware, I guess it should be possible to have a
global variable and/or constants in a memory. Is it possible to design
hardware in such a way using Verilog?
 
On Mon, 07 Mar 2005 20:58:26 -0500, thomasc wrote:

Thanks for the reply.

Even if I imagine a hardware, I guess it should be possible to have a
global variable and/or constants in a memory. Is it possible to design
hardware in such a way using Verilog?
Click to expand...
It's certainly possible to distribute a set of signals through
your code. Say you have a hierarchy like this:

top
core
cpu
alu
control
registers
uart
tx
rx
clkgen

if you had a bus coming from top.core.cpu.alu you would make it
an output port. In top.core.cpu you would hook up the output port
from the alu to an output port also and run it up to the top.core
level. You might also hook it to an input port on the registers
or control.

Then you could feed the bus as an input port back down into
top.core.uart.tx and rx and clkgen.

It ends up being a lot of 'plumbing', but because of the way
logic synthesizers are used, and the way blocks are laid out
in real chips, most of the time those wires really exist and
need to be accounted for - they have capacitance and inductance
and if you use too many of them your design slows down or area
used goes up.
 
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