global records (xilinx isim)

[Ken Cecka]

Hi All,

I've got a testbench framework I've been using for a while now in Xilinx ISim and it's been working well, but I recently tried to migrate it to another project and ran into all kinds of problems with ISim hanging. I finally tracked it down to a signal I had removed because it was unused.

I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, but I thought I'd ask about it here first in case I'm doing something horribly abusive/invalid with the language. In the code pasted below, things work fine as long as dummy is present. If I comment out dummy, ISim hangs for several minutes and then exits.

Other points of interest:
- if I change 'r' to an integer, isim never hangs
(irrespective of dummy)
- if I leave 'r' as a record but put it inside tb, isim always hangs
(irrespective of dummy)

Ken

-------------------------------------------------------------------------------

PACKAGE pkg IS

TYPE rec IS
RECORD
sig : INTEGER;
END RECORD;

SIGNAL r : rec;

COMPONENT dut IS PORT ( r : IN rec );
END COMPONENT;

END pkg;

-------------------------------------------------------------------------------

USE WORK.pkg.ALL;

ENTITY dut IS PORT ( r : IN rec );
END dut;

ARCHITECTURE model OF dut IS
SIGNAL dummy : INTEGER;
BEGIN
END;

-------------------------------------------------------------------------------

USE WORK.pkg.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE model OF tb IS
BEGIN

WRAPPER : dut PORT MAP (r => r);

PROCESS
BEGIN
WAIT FOR 1500 ns;
ASSERT (FALSE) REPORT "Done!" SEVERITY NOTE;
WAIT;
END PROCESS;

END;

 

[Brian Drummond]

On Sat, 25 Apr 2009 23:11:27 GMT, Ken Cecka <ceckak@alumni.washington.edu>
wrote:

Hi All,

I've got a testbench framework I've been using for a while now in Xilinx ISim and it's been working well, but I recently tried to migrate it to another project and ran into all kinds of problems with ISim hanging. I finally tracked it down to a signal I had removed because it was unused.

I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, but I thought I'd ask about it here first in case I'm doing something horribly abusive/invalid with the language.

ISIM still has many issues with "rarely used" parts of VHDL (which of course, I
seem to use a lot of the time). At one point I had eight Webcases open, mostly
on ISIM, which resulted in five or six CRs to hopefully resolve some of the
problems in upcoming releases.

This one clearly needs to be a webcase, and pursued (sometimes it takes
persistence, depending on the support engineer you get. It's a bad sign if they
reply in Lolcat...) until you get a CR. Even if you were doing something illegal
here, ISIM should detect it and produce an error message rather than hanging (or
aborting with SIGSEGV/Access Violation).

But I believe Xilinx are committed to major improvements in ISIM, and in my
experience, once you can drive round the minefields it's becoming a useful tool.

- Brian

 

[Ken Cecka]

Brian Drummond wrote:

On Sat, 25 Apr 2009 23:11:27 GMT, Ken Cecka <ceckak@alumni.washington.edu
wrote:

Hi All,

I've got a testbench framework I've been using for a while now in Xilinx
ISim and it's been working well, but I recently tried to migrate it to
another project and ran into all kinds of problems with ISim hanging. I
finally tracked it down to a signal I had removed because it was unused.

I've boiled it down to a minimal testcase which I'll be submitting to
Xilinx, but I thought I'd ask about it here first in case I'm doing
something horribly abusive/invalid with the language.

ISIM still has many issues with "rarely used" parts of VHDL (which of
course, I seem to use a lot of the time). At one point I had eight
Webcases open, mostly on ISIM, which resulted in five or six CRs to
hopefully resolve some of the problems in upcoming releases.

This one clearly needs to be a webcase, and pursued (sometimes it takes
persistence, depending on the support engineer you get. It's a bad sign if
they reply in Lolcat...) until you get a CR. Even if you were doing
something illegal here, ISIM should detect it and produce an error message
rather than hanging (or aborting with SIGSEGV/Access Violation).

I'll definitely be filing one - I've gotten fairly good responses form Xilinx in the past. Just figured it was worth getting some feedback here first - I've learned VHDL more from experimentation and examples than from rigorous study of the language, and that sometimes gets me in trouble.

But I believe Xilinx are committed to major improvements in ISIM, and in
my experience, once you can drive round the minefields it's becoming a
useful tool.

- Brian

 

[Mike Treseler]

Ken Cecka wrote:

I've boiled it down to a minimal testcase which I'll be submitting to Xilinx,
but I thought I'd ask about it here first in case
I'm doing something horribly abusive/invalid with the language.

My local language expert is vsim,
and he has no complaints.
Good luck.

-- Mike Treseler
______________________________________________________
# vsim -c tb
# ** Note: (vsim-3812) Design is being optimized...
# // ModelSim SE 6.2a Jun 16 2006 Linux 2.6.25.16-0.1-default

# Loading work.pkg
# Loading work.tb(model)
# Loading work.dut(model)
VSIM 1> run 1 ms
# ** Note: Done!
# Time: 1500 ns Iteration: 0 Instance: /tb
VSIM 2>

 

[JimLewis]

Hi Ken,

I've got a testbench framework I've been using for a while now in Xilinx ISim and it's been working well, but I recently tried to migrate it to another project and ran into all kinds of problems with ISim hanging.  I finally tracked it down to a signal I had removed because it was unused.

I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, but I thought I'd ask about it here first in case I'm doing something horribly abusive/invalid with the language.  

ISIM still has many issues with "rarely used" parts of VHDL (which of course, I
seem to use a lot of the time). At one point I had eight Webcases open, mostly
on ISIM, which resulted in five or six CRs to hopefully resolve some of the
problems in upcoming releases.

I consider record INOUT to be essential for writing transaction level
models in VHDL.
In my testbench I use records whose elements are resolved types and
initialize the
ports. In my case the records are exclusively on the testbench
entities.

For more details, see the 2nd half of the paper titled, "Accelerating
Verification
Through Pre-Use of System-Level Testbench Components" which is at:

http://www.synthworks.com/papers/index.htm

Cheers,
Jim