U
unfrostedpoptart
Guest
Related to my questions about parameters / include files for module port headers, I just ran into something that I don't think should work, but does - which is good if confusing:
I have a structure defined in an include file that I use as a type of port in my module. Therefore, I have to include the header file before the module keyword. However, this structure uses parameters. So, I have to include my parameter header file at the beginning of the structure header file. This means the parameters aren't defined inside a module. I didn't think that was legal.
What's going on here? Is this new in System Verilog? Is there some back-referencing going on? I have the 1800-2009 LRM, but don't know where to look for this. As an aside - you'd think for almost $300, the LRM PDF would have a PDF table of contents!!!
David
I have a structure defined in an include file that I use as a type of port in my module. Therefore, I have to include the header file before the module keyword. However, this structure uses parameters. So, I have to include my parameter header file at the beginning of the structure header file. This means the parameters aren't defined inside a module. I didn't think that was legal.
What's going on here? Is this new in System Verilog? Is there some back-referencing going on? I have the 1800-2009 LRM, but don't know where to look for this. As an aside - you'd think for almost $300, the LRM PDF would have a PDF table of contents!!!
David