Global counter in FPGAs

[kb33]

Hi,

This posting is to get some insight into the use of global counters in
FPGAs. I would like to start with the following questions, please feel
free to add on to the list...

1. Is it common to use a global counter in FPGA (or for that matter,
ASIC, or any hardware design) ?
2. Is there anything wrong with using it - synthesis issues, and so on?
3. Is there an alternative to global counters?
4. Does their place and route pose any problems/issues ?

Thanks
kb33