Glitchs at the output of a latch

[Patrick]

hello,

I synthesis a simple latch of 18 bits on a altera stratix fpga with
quartus II 4.0.

I use two sort of implementation :

1 - Latch_18 : process (clock_smp,reset)
begin
if (clock_smp'event and clock_smp='1') then
if reset = '1' then out_filter <= "000000000000000000";
else out_filter <= resul;
end if;
end if;
end process Latch_18;

2 - With the Megafunction Latch LPM of Altera

The simulation after synthesis show that the data on the 18 bit bus
arrive 7 ns after the rising edge of clock_smp AND they arrived within
ŕ 1 ns time, so that generate glitchs of 1 ns large..

What's happen ? I put with latche_18 on the output of a RIF filter for
cancelling glitches but it doesn't work correctly...

Thanks for subjection

 

[Nicolas Matringe]

Patrick a écrit:

The simulation after synthesis show that the data on the 18 bit bus
arrive 7 ns after the rising edge of clock_smp AND they arrived within
ŕ 1 ns time, so that generate glitchs of 1 ns large..

Maybe a stupid question but what is your simulation resolution? Make
sure you don't simulate with a 1ns reslution.


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[paris]

"Patrick" <patrick.melet@dmradiocom.fr> escribió en el mensaje
news:54b3002.0405260602.321f1762@posting.google.com...

hello,

I synthesis a simple latch of 18 bits on a altera stratix fpga with
quartus II 4.0.

I use two sort of implementation :

1 - Latch_18 : process (clock_smp,reset)
begin
if (clock_smp'event and clock_smp='1') then
if reset = '1' then out_filter <= "000000000000000000";
else out_filter <= resul;
end if;
end if;
end process Latch_18;

2 - With the Megafunction Latch LPM of Altera

The simulation after synthesis show that the data on the 18 bit bus
arrive 7 ns after the rising edge of clock_smp AND they arrived within
ŕ 1 ns time, so that generate glitchs of 1 ns large..

im not sure if i understood your problem, but is it that the different bits
that form the 18bit bus are not arriving at the same time, but within a std
deviation of 1ns around 7ns, is that right? if it is, then it's due to
routing delay and as long as your design is synchronous, you shouldnt have
any trouble as the data should be already stabilised when the next clock
edge arrives and latches the data for the next stage.

also i believe that modelsim has an option to turn off glitch generation,
but i've never used.

What's happen ? I put with latche_18 on the output of a RIF filter for
cancelling glitches but it doesn't work correctly...

Thanks for subjection

 

[Patrick]

Nicolas Matringe <matringe.nicolas@numeri-cable.fr> wrote in message news:<40B4AAA2.6000104@numeri-cable.fr>...

Patrick a écrit:

The simulation after synthesis show that the data on the 18 bit bus
arrive 7 ns after the rising edge of clock_smp AND they arrived within
ŕ 1 ns time, so that generate glitchs of 1 ns large..

Maybe a stupid question but what is your simulation resolution? Make
sure you don't simulate with a 1ns reslution.

Of course the simulator have a time step of 1 ps !!! Sorry...

 

[Patrick]

Hello,

In fact, the problem is due to the I/O Pads, because the signal before
the latch and after the latch comes out the fpga that result in a
propagation time of 7 ns with delta time 400 ps

and in an internal latche (without pads) the propagation delay becomes
3 ns with a delta time of 40 ps.... that looks better...

 

[Thomas Stanka]

Hello,

"paris" <asdjflksakjdfmalaka@email.it> wrote:

"Patrick" <patrick.melet@dmradiocom.fr
The simulation after synthesis show that the data on the 18 bit bus
arrive 7 ns after the rising edge of clock_smp AND they arrived within
ŕ 1 ns time, so that generate glitchs of 1 ns large..


im not sure if i understood your problem, but is it that the different bits
that form the 18bit bus are not arriving at the same time, but within a std
deviation of 1ns around 7ns, is that right? if it is, then it's due to
routing delay and as long as your design is synchronous, you shouldnt have
any trouble as the data should be already stabilised when the next clock
edge arrives and latches the data for the next stage.

also i believe that modelsim has an option to turn off glitch generation,
but i've never used.

It has, but that is no glitch problem, this is a problem of routing
delays.
Glitch means a signal going high and back low (or vice versa) within a
very short period due to differnent signal routing delays for the same
signal.
(eg. the output of a nand with both inputs changing its value with a
very small delay).

If you have a problem with 1ns deviation, you should place by hand to
optimize the timing. The reachable value depends strongly on the
technic of your device (and your patience, this job might be very
nasty).

bye Thomas