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It is really hard to get rid of glitches with combinatorial logic. IfHi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
Then generally how do we do it if we have to get rid of glitches andOn Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
Hi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches (assuming
timing constraints are met), but your gray code will be one clock
behind the binary code.
Andy
Then in that case building a genric gray counter would be bitgtalk.nik...@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches
(assuming timing constraints are met), but your gray code will be
one clock behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Build a Gray counter instead of a binary one. If you need a binary value,
convert Gray->binary instead of the other way round.
John
--
John Penton, posting as an individual unless specifically indicated
otherwise.- Hide quoted text -
- Show quoted text -
gray -> binary -> +1 -> gray -> regOn Sep 12, 9:37 pm, "John Penton" <john.pen...@arm.com> wrote:
gtalk.nik...@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches
(assuming timing constraints are met), but your gray code will be
one clock behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Build a Gray counter instead of a binary one. If you need a binary value,
convert Gray->binary instead of the other way round.
John
--
John Penton, posting as an individual unless specifically indicated
otherwise.- Hide quoted text -
- Show quoted text -
Then in that case building a genric gray counter would be bit
difficult.
Could you build the binary->gray converter to look ahead, and convertOn Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
Hi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches (assuming
timing constraints are met), but your gray code will be one clock
behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
My apologies, I forgot this was the verilog and not the VHDL group.On Sep 12, 11:02 am, gtalk.nik...@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
Hi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches (assuming
timing constraints are met), but your gray code will be one clock
behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Could you build the binary->gray converter to look ahead, and convert
the binary+1 value, then register it? This seem slike it should let
everything be registered and also keep the binary and gray values in
sync.
process(clk)
begin
if rising_edge(clk) then
binary <= binary + 1;
gray <= bin2gray(binary+1);
end if;
end process;
Dave
On Sep 16, 3:34 pm, Dave <dhsch...@gmail.com> wrote:
On Sep 12, 11:02 am, gtalk.nik...@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
Hi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches (assuming
timing constraints are met), but your gray code will be one clock
behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Could you build the binary->gray converter to look ahead, and convert
the binary+1 value, then register it? This seem slike it should let
everything be registered and also keep the binary and gray values in
sync.
process(clk)
begin
if rising_edge(clk) then
binary <= binary + 1;
gray <= bin2gray(binary+1);
end if;
end process;
Dave
My apologies, I forgot this was the verilog and not the VHDL group.
I'm pretty weak in verilog, but I'll try:
always@posedge(clk)
begin
binary <= binary + 1;
gray <= gray2bin(binary+1);
end
thanks for the replies friends, it helped....On Sep 16, 2:42 pm, Dave <dhsch...@gmail.com> wrote:
On Sep 16, 3:34 pm, Dave <dhsch...@gmail.com> wrote:
On Sep 12, 11:02 am, gtalk.nik...@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
Hi,
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??
It is really hard to get rid of glitches with combinatorial logic.. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches (assuming
timing constraints are met), but your gray code will be one clock
behind the binary code.
Andy
Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Could you build the binary->gray converter to look ahead, and convert
the binary+1 value, then register it? This seem slike it should let
everything be registered and also keep the binary and gray values in
sync.
process(clk)
begin
if rising_edge(clk) then
binary <= binary + 1;
gray <= bin2gray(binary+1);
end if;
end process;
Dave
My apologies, I forgot this was the verilog and not the VHDL group.
I'm pretty weak in verilog, but I'll try:
always@posedge(clk)
begin
binary <= binary + 1;
gray <= gray2bin(binary+1);
end
...
gray <= bin2gray(binary + 1);
...
Andy- Hide quoted text -
- Show quoted text -