glitch / synthesis problem

[quiz]

the function is:

async latch

| D | En | Q(out) |
---------------------------
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 0 | d.care | Q(delta-1) |


Q = En*D + En_ * Q(t-1)

(without clock)

where is the glitch problem ?
How would you implement it without any glitch problem ?

thanks

 

[Marcin]

Hi,

module latch(d,en,q,q_bar);
input d, en;
output q,q_bar;
wire #20 imp1 = d & en; //here is the problem
wire imp2 = ~en & q;

//imp2 should be slower than imp1 to avoid glitch

assign q = imp1 | imp2;
assign q_bar = ~q;
endmodule

module test_glitch;
reg d,en;
wire q,q_bar;

latch UUT(d,en,q,q_bar);

initial begin
d = 0;
en = 0;
#100;
d = 1;
en = 1;//glitch
#100;
en = 0;
#100;
en = 1;//glitch
#100;

end
endmodule

Regards,

Marcin
snzv@hotmail.com (quiz) wrote in message news:<863742e.0312080507.44c32840@posting.google.com>...

the function is:

async latch

| D | En | Q(out) |
---------------------------
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 0 | d.care | Q(delta-1) |


Q = En*D + En_ * Q(t-1)

(without clock)

where is the glitch problem ?
How would you implement it without any glitch problem ?

thanks