Guest
Hi
I'm developing a Pulse-Width-Modulation (PWM) scheme on a Xilinx
spartan 3 digilent demo board to perform sinusoidal current control in
a 3 phase motor. I've managed to just about get it working apart from
some strange behaviour where something unknown causes a glitch and
this results in a spike in the current in the motor. The interesting
thing is that during the course of trying to find the problem I have
wired various signals internal to the FPGA to output pins to view on a
scope. In doing this (purely connecting internal signals to the IO
pins) the problem has been cured. I'm guessing therefore that this is
a timing issue or could anyone suggest an alternative cause? Is there
a method of setting timing constraints for internal signals in ISE?
(I can set timing constraints for inputs and outputs but can't find
anything to set timing constraints on internal signals)
The block proceeding the signal which is routed to the IO (to cure the
problem) is a lookup table that compares a timer count signal with
duty times and produces a control signal. The VHDL code for this
block is:
begin
process (count, d1, d1_d2)
begin
if (count <= d1) then
vector_control <= "00";
elsif ((count > d1) AND (count <= d1_d2)) then
vector_control <= "01";
else vector_control <= "10";
end if;
end process;
ISE has implemented this as some magnitude comparators and a ROM
(implemented in a LUT rather than blockram)
This part of the system is combinatorial and not clocked but inserting
a clocked register on the output of this block does not help.
Any suggestions or comments greatly appreciated.
Steve Minshull
I'm developing a Pulse-Width-Modulation (PWM) scheme on a Xilinx
spartan 3 digilent demo board to perform sinusoidal current control in
a 3 phase motor. I've managed to just about get it working apart from
some strange behaviour where something unknown causes a glitch and
this results in a spike in the current in the motor. The interesting
thing is that during the course of trying to find the problem I have
wired various signals internal to the FPGA to output pins to view on a
scope. In doing this (purely connecting internal signals to the IO
pins) the problem has been cured. I'm guessing therefore that this is
a timing issue or could anyone suggest an alternative cause? Is there
a method of setting timing constraints for internal signals in ISE?
(I can set timing constraints for inputs and outputs but can't find
anything to set timing constraints on internal signals)
The block proceeding the signal which is routed to the IO (to cure the
problem) is a lookup table that compares a timer count signal with
duty times and produces a control signal. The VHDL code for this
block is:
begin
process (count, d1, d1_d2)
begin
if (count <= d1) then
vector_control <= "00";
elsif ((count > d1) AND (count <= d1_d2)) then
vector_control <= "01";
else vector_control <= "10";
end if;
end process;
ISE has implemented this as some magnitude comparators and a ROM
(implemented in a LUT rather than blockram)
This part of the system is combinatorial and not clocked but inserting
a clocked register on the output of this block does not help.
Any suggestions or comments greatly appreciated.
Steve Minshull