Glitch on clock pin

A

arant

Guest
We had a basic doubt about the D-flop functionality it would be great
if anyone could reply to the query

In case the clock pin of a clock has a glitch but the D pin of the
flop remains at a stable logic value either 1/0 will the output Q of
the flop produce a glitch ?

* In case a glitch is not produced, is there any possibility of an
X at Q pin on the next active edge of the clock due the recirculation
in the slave stage due to clock glitch

Thanks in advance
Arant
 
On Dec 8, 6:53 am, arant <arant.agra...@gmail.com> wrote:
We had a basic doubt about the D-flop functionality it would be great
if anyone could reply to the query

In case the clock pin of a clock has a glitch but the D pin of the
flop remains at a stable logic value either 1/0 will the output Q of
the flop produce a glitch ?

    * In case a glitch is not produced, is there any possibility of an
X at Q pin on the next active edge of the clock due the recirculation
in the slave stage due to clock glitch

Thanks in advance
Arant
This seems to be an issue of the actual flip-flop design rather than
a Verilog or modelling issue. It is not obvious that different D
flip-flop designs would behave the same for the glitch case. For
example it seems probable that some designs could be guaranteed
not to glitch on a short clock pulse _if_ the D is at the same
logic level as Q. Whether there is a glitch or change of state
on the output when D is not the same as Q would depend on the
design. In the old TTL days, the device manufacturers would give
a gate-level schematic of the D-flip-flop, but even then it was
not necessarily the actual implementation inside the device. I
remember a very elegant design for the 7474 flip-flop using 6
3-input NAND gates shown in the TI TTL data book.

Even with a schematic there are regions where you don't quite
know what will happen. For example if the clock glitch is
short enough that some gates might filter it out but others
might not, you can't really predict the outcome. Obviously
a short enough glitch will be filtered out from all gates
and then no change would occur.

With CMOS logic came transfer gates, and the schematics were
eventually dropped from the books, so you don't always know
what the device will do when operated outside the recommended
timing characteristics.

Your question about the "X" on the next clock edge, seems to
imply you are working with a model of some sort. Even models
from the device manufacturers may not represent the actual
characteristics of the device under unusual input timing.
So for instance if your clock glitch was short enough to
avoid upsetting any internal nodes of the flip-flop, the
model still may not represent this correctly and could look
at the following clock edge as coming too soon to meet
the device Fmax.
 
On Dec 9, 1:33 am, gabor <ga...@alacron.com> wrote:
On Dec 8, 6:53 am, arant <arant.agra...@gmail.com> wrote:

We had a basic doubt about the D-flop functionality it would be great
if anyone could reply to the query

In case the clock pin of a clock has a glitch but the D pin of the
flop remains at a stable logic value either 1/0 will the output Q of
the flop produce a glitch ?

    * In case a glitch is not produced, is there any possibility of an
X at Q pin on the next active edge of the clock due the recirculation
in the slave stage due to clock glitch

Thanks in advance
Arant

This seems to be an issue of the actual flip-flop design rather than
a Verilog or modelling issue.  It is not obvious that different D
flip-flop designs would behave the same for the glitch case.  For
example it seems probable that some designs could be guaranteed
not to glitch on a short clock pulse _if_ the D is at the same
logic level as Q.  Whether there is a glitch or change of state
on the output when D is not the same as Q would depend on the
design.  In the old TTL days, the device manufacturers would give
a gate-level schematic of the D-flip-flop, but even then it was
not necessarily the actual implementation inside the device.  I
remember a very elegant design for the 7474 flip-flop using 6
3-input NAND gates shown in the TI TTL data book.

Even with a schematic there are regions where you don't quite
know what will happen.  For example if the clock glitch is
short enough that some gates might filter it out but others
might not, you can't really predict the outcome.  Obviously
a short enough glitch will be filtered out from all gates
and then no change would occur.

With CMOS logic came transfer gates, and the schematics were
eventually dropped from the books, so you don't always know
what the device will do when operated outside the recommended
timing characteristics.

Your question about the "X" on the next clock edge, seems to
imply you are working with a model of some sort.  Even models
from the device manufacturers may not represent the actual
characteristics of the device under unusual input timing.
So for instance if your clock glitch was short enough to
avoid upsetting any internal nodes of the flip-flop, the
model still may not represent this correctly and could look
at the following clock edge as coming too soon to meet
the device Fmax.
Gabor,Thanks for the detailed reply it was more than I bargained
for ...

My query was basically targeted towards people who are into CMOS level
design of
Flops and have better understanding of the library elements in
existence today (~65nm)

Looking at the data-sheets of various manufacturers, they seem pretty
vague on this kind
of behavior.
According to my understanding no timing laws are getting violated here
as there is basically 'NO'
timing happening here (i.e no data sampling) so there should not be
any question of a glitch.

I think someone who works at a CMOS transistor level can better shed
light on this.

-- arant
 
On Mon, 8 Dec 2008 23:57:52 -0800 (PST), arant
<arant.agrawal@gmail.com> wrote:

My query was basically targeted towards people who are into CMOS level
design of
Flops and have better understanding of the library elements in
existence today (~65nm)

Looking at the data-sheets of various manufacturers, they seem pretty
vague on this kind
of behavior.
According to my understanding no timing laws are getting violated here
as there is basically 'NO'
timing happening here (i.e no data sampling) so there should not be
any question of a glitch.

I think someone who works at a CMOS transistor level can better shed
light on this.
Actually this has nothing to do with CMOS design. The flop can be
implemented with CMOS, CML or dynamic logic or any other technology. A
flop is about storing the value of its input at some point and for
that to work reliably a decision has to be made and a node has to be
charged based on the decision. If the input is not disagreeing with
the currently stored charge, whether the sampling waveform propagates
to the input of the storage doesn't (shouldn't) matter. For this to
work the condition is a little stronger than you suggested. Not only
should the D input stay stable but it should also stay at the value
currently designated by the Q output. In that case it should not
matter what the clock input is doing for a well designed flop and the
output should stay at its current value. Of course if the stored value
and the current D input are different then a glitch on the CLK input
may not be able to set the flop to its correct value even though the D
input may have been generated according to the setup constraint. There
are also minimum clock high and low constraints for the sampling to
occur correctly in addition to setup/hold constraints.


Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 

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