A
arant
Guest
We had a basic doubt about the D-flop functionality it would be great
if anyone could reply to the query
In case the clock pin of a clock has a glitch but the D pin of the
flop remains at a stable logic value either 1/0 will the output Q of
the flop produce a glitch ?
* In case a glitch is not produced, is there any possibility of an
X at Q pin on the next active edge of the clock due the recirculation
in the slave stage due to clock glitch
Thanks in advance
Arant
if anyone could reply to the query
In case the clock pin of a clock has a glitch but the D pin of the
flop remains at a stable logic value either 1/0 will the output Q of
the flop produce a glitch ?
* In case a glitch is not produced, is there any possibility of an
X at Q pin on the next active edge of the clock due the recirculation
in the slave stage due to clock glitch
Thanks in advance
Arant