glitch free clock switch for more than two clocks

[Andy Luotto]

hello
i need to switch more than two clocks. should i cascade two or more
clock switchers (e.g http://www.vlsi-world.com/images/stories/EDA_topics/clock_switch/safe_clock_switch_circuit.png)
or design a single switch? how to extend the 2 clock design to three
or more clock, maybe using verilog 2001 generates?
rhx in advan to whoever will reply

 

[gabor]

On Oct 19, 11:30 am, Andy Luotto <andyluo...@excite.com> wrote:

hello
i need to switch more than two clocks. should i cascade two or more
clock switchers (e.g  http://www.vlsi-world.com/images/stories/EDA_topics/clock_switch/safe...)
or design a single switch? how to extend the 2 clock design to three
or more clock, maybe using verilog 2001 generates?
rhx in advan to whoever will reply

I'm pretty sure there's an error in the diagram. It looks
to me like the final OR gate on clk_a should go to the Q
output of the right top flip-flop, not the Q bar. In any
case this sort of circuit can be extended for more inputs.

The flops on the right are clock disable functions for
each source. They are active when the associated clock
is not selected, or any other clock has been selected
recently. Running through a flop on each clock domain
guarantees that the newly disabled clock has been gated
out before the new clock gates in and you don't get
runt pulses.

There is a down side to this form of clock select logic.
It only works when all of the clocks are free-running.
Gate off an active clock input, and the selection can
get stuck.

Regards,
Gabor