gigabit ethernet problem

S

salimbaba

Guest
Hi,
I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with
national Gigabit PHYs. So i receive a packet from phy A and transmit it t
PHY B and vice versa. Now the problem i am facing is that one of the byte
in the packet randomly gets corrupt after a while..

First the packet drop was very frequent at high speeds, then i checked th
power requirements of my PHYs and got to know that my regulator couldn'
source that much current. Then i changed the regulator and now the proble
occurs very rarely or it doesnt occur at all.

I have some checks in the RTL to identify if the error is FCS or buffe
overflow.So every time the packet drops, my fcs flag is raised. So i viewe
the incoming packet and saw that it always had some random corrupt byte
Like i was sending packets with known pattern, so after a while some rando
byte is getting corrupt. I don't know what to look for from now onwards.
I thought maybe it was the heat issue so used heat gun but nah it wasn'
the heat problem.
My ground noise is 80mv peak-to-peak.

Need some pointers..

Regards


---------------------------------------
Posted through http://www.FPGARelated.com
 
hi
have your problem solved, cause i 'm facing the same problem with Realte
RTL8201 chip at the receive section,i connected RXD to TXD and RXDV to TX
to test the chip in loopback through fpga xilinx spartan 3 xc3s400, in thi
test i got 4 out of 50 packets with fcs error at the pc. what's the issue?
tnx for any help
Hi,
I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2
national Gigabit PHYs. So i receive a packet from phy A and transmit i
to
PHY B and vice versa. Now the problem i am facing is that one of th
bytes
in the packet randomly gets corrupt after a while..

First the packet drop was very frequent at high speeds, then i checke
the
power requirements of my PHYs and got to know that my regulator couldn't
source that much current. Then i changed the regulator and now th
problem
occurs very rarely or it doesnt occur at all.

I have some checks in the RTL to identify if the error is FCS or buffer
overflow.So every time the packet drops, my fcs flag is raised. So
viewed
the incoming packet and saw that it always had some random corrupt byte.
Like i was sending packets with known pattern, so after a while som
random
byte is getting corrupt. I don't know what to look for from now onwards.
I thought maybe it was the heat issue so used heat gun but nah it wasn't
the heat problem.
My ground noise is 80mv peak-to-peak.

Need some pointers..

Regards


---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
On 22/09/2011 20:21, salimbaba wrote:
Hi,
I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2
national Gigabit PHYs. So i receive a packet from phy A and transmit it to
PHY B and vice versa. Now the problem i am facing is that one of the bytes
in the packet randomly gets corrupt after a while..

First the packet drop was very frequent at high speeds, then i checked the
power requirements of my PHYs and got to know that my regulator couldn't
source that much current. Then i changed the regulator and now the problem
occurs very rarely or it doesnt occur at all.

I have some checks in the RTL to identify if the error is FCS or buffer
overflow.So every time the packet drops, my fcs flag is raised. So i viewed
the incoming packet and saw that it always had some random corrupt byte.
Like i was sending packets with known pattern, so after a while some random
byte is getting corrupt. I don't know what to look for from now onwards.
I thought maybe it was the heat issue so used heat gun but nah it wasn't
the heat problem.
My ground noise is 80mv peak-to-peak.

Need some pointers..

Regards


---------------------------------------
Posted through http://www.FPGARelated.com
Can you please describe the hardware setup in more detail - is it your
Click to expand...
own board or a known good board. Has this hardware setup ever worked (ie
been error free ?).
Is there any pattern in the 'random' corruption (eg is it always bit 0
or a 1 seen as 0 (or a 0 seen as 1) etc etc. Is it always the nth byte
in a packet etc.
Michael Kellett
 
i designed and rout the pcb board,i have one RTL8201BL as lan phy layer an
Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don'
have any error in sending packets, i tested transmit section at 95
bandwidth without a packet loss, but at receive there are random erro
receiving packets. the bytes that are corrupt are also random and does no
have a pattern. only when the packet length become large(about 1400 Bytes)
the error occur more frequent about (3-4 out of 20 packets),
i don't know how i can debug the problem,
tnx in advanced for help :)



---------------------------------------
Posted through http://www.FPGARelated.com
 
On 21/02/2012 05:04, nba83 wrote:
i designed and rout the pcb board,i have one RTL8201BL as lan phy layer and
Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't
have any error in sending packets, i tested transmit section at 95%
bandwidth without a packet loss, but at receive there are random error
receiving packets. the bytes that are corrupt are also random and does not
have a pattern. only when the packet length become large(about 1400 Bytes),
the error occur more frequent about (3-4 out of 20 packets),
i don't know how i can debug the problem,
tnx in advanced for help :)



---------------------------------------
Posted through http://www.FPGARelated.com
I can only make the most general suggestions. How are you generating the
Click to expand...
test packets - are you sure they are good. Can you check the signal
integrity on either side of the PHY.
Are the errors similar to those you got when the power supply was poor.
Is the position of the errored byte at the start or end of the packet or
just anywhere. Do you ever get more than one error per packet. Does it
get worse or better with any boundary cases: ie does it never fail with
a minimum length packet or fail lots more often with maximum length.
Is there any sensitivity to packet contents.
Is there any sensitivity to rate of packets.

MK
 
On Feb 20, 9:04 pm, "nba83"
<nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
i designed and rout the pcb board,i have one RTL8201BL as lan phy layer and
Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't
have any error in sending packets, i tested transmit section at 95%
bandwidth without a packet loss, but at receive there are random error
receiving packets. the bytes that are corrupt are also random and does not
have a pattern. only when the packet length become large(about 1400 Bytes),
the error occur more frequent about (3-4 out of 20 packets),
i don't know how i can debug the problem,
tnx in advanced for help :)

---------------------------------------
Posted throughhttp://www.FPGARelated.com
Click to expand...
Have you checked all your timing? Making setup/hold times for the Rx
side of GigE can be tough with a Spartan. Been there, done that, you
need to be very careful.

John P
 
On Feb 20, 9:04=A0pm, "nba83"
nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
i designed and rout the pcb board,i have one RTL8201BL as lan phy laye
a=
nd
Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't
have any error in sending packets, i tested transmit section at 95%
bandwidth without a packet loss, but at receive there are random error
receiving packets. the bytes that are corrupt are also random and doe
no=
t
have a pattern. only when the packet length become large(about 140
Bytes=
),
the error occur more frequent about (3-4 out of 20 packets),
i don't know how i can debug the problem,
tnx in advanced for help :)

---------------------------------------
Posted throughhttp://www.FPGARelated.com

Have you checked all your timing? Making setup/hold times for the Rx
side of GigE can be tough with a Spartan. Been there, done that, you
need to be very careful.

John P
Click to expand...
no i don't know how to do that? i don't know what are setup/hold times fo
Rx, and my Phy layer is 100MHz not Gig, I used RTL8201BL and i wrote
simple loopback program in which i connected RXDV to TXE and RXD to TXD a
the corresponding TXCLK and RXCLK, do i need to do some timing for thi
simple program??
here is my code:

always @ (posedge RTL_RXCLK)
begin
data <= RTL_RXD;
en <= RTL_RXDV;
end

always @ (posedge RTL_TXCLK)
begin
RTL_TXD_I <= data;
RTL_TXE_I <= en;
end


---------------------------------------
Posted through http://www.FPGARelated.com
 
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com...
here is my code:

always @ (posedge RTL_RXCLK)
begin
data <= RTL_RXD;
en <= RTL_RXDV;
end

always @ (posedge RTL_TXCLK)
begin
RTL_TXD_I <= data;
RTL_TXE_I <= en;
end
Click to expand...
Huh? I havent been reading this thread in details, but how are these clocks
syncronized? Maybe they arent, hence your problem.
 
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com...
here is my code:

always @ (posedge RTL_RXCLK)
begin
data <= RTL_RXD;
en <= RTL_RXDV;
end

always @ (posedge RTL_TXCLK)
begin
RTL_TXD_I <= data;
RTL_TXE_I <= en;
end

Huh? I havent been reading this thread in details, but how are thes
clocks
syncronized? Maybe they arent, hence your problem.




i write it in two processes to ensure if the two clk are not syncronize
Click to expand...
the data won't read and transmited bad.

---------------------------------------
Posted through http://www.FPGARelated.com
 
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:dtKdneQMFslBK9nSnZ2dnUVZ_hudnZ2d@giganews.com...
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com...
here is my code:

always @ (posedge RTL_RXCLK)
begin
data <= RTL_RXD;
en <= RTL_RXDV;
end

always @ (posedge RTL_TXCLK)
begin
RTL_TXD_I <= data;
RTL_TXE_I <= en;
end

Huh? I havent been reading this thread in details, but how are these
clocks
syncronized? Maybe they arent, hence your problem.




i write it in two processes to ensure if the two clk are not syncronized
the data won't read and transmited bad.
Click to expand...
So you are trying to send some data grabbed in one clock domain into a
different? You know that will fail?
If the clocks are almost similar, it will work for periods when the clock
phases are close.
If txclk is derived from rxclk, you may get it to work, but first make a
common domain.
 
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:dtKdneQMFslBK9nSnZ2dnUVZ_hudnZ2d@giganews.com...
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote i
message
news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com...
here is my code:

always @ (posedge RTL_RXCLK)
begin
data <= RTL_RXD;
en <= RTL_RXDV;
end

always @ (posedge RTL_TXCLK)
begin
RTL_TXD_I <= data;
RTL_TXE_I <= en;
end

Huh? I havent been reading this thread in details, but how are these
clocks
syncronized? Maybe they arent, hence your problem.




i write it in two processes to ensure if the two clk are no
syncronized
the data won't read and transmited bad.

So you are trying to send some data grabbed in one clock domain into a
different? You know that will fail?
If the clocks are almost similar, it will work for periods when the cloc

phases are close.
If txclk is derived from rxclk, you may get it to work, but first make a
common domain.




tnx for your comment, so what should i do? i have tested the following cod
Click to expand...
too, but still i have error in receiving packets.
assign RTL_TXE=RTL_RXDV;
assign RTL_TXD=RTL_RXD;

tnx in advanced for help :)
Neda Baheri

---------------------------------------
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"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
tnx for your comment, so what should i do? i have tested the following
code
too, but still i have error in receiving packets.
assign RTL_TXE=RTL_RXDV;
assign RTL_TXD=RTL_RXD;
Click to expand...
If your receiver gives you a clock, put that on a global clock, work with
the data in this domain and also feed the transmitter with it. Be careful
with timing. I would need your schematic diagram to tell more.

tnx in advanced for help :)
Neda Baheri
Click to expand...
NP
 
My problem got solved, had to do the timing analysis once again. Althoug
XST wasn't reporting any timing failures, but I was on boundary, so once i
a while I was getting the issue.

As far as your issue is concerned, what you are missing as pointed out b
NP is that you have two clock domains. So, you need to sync these two cloc
domains. I think your phy is giving you both TXCLK and RXCLK at 25Mhz, fo
100Mbps, correct me if i am wrong.

The best thing would be use a buffer at the incoming interface, write th
data to the FIFO on RXCLK and after 4-5 writes, read the packet bytes a
TXCLK.
Also, you do know how the ethernet works, right ? like in 100Mbps you hav
to deal with a nibble at a time, and in 1000Mbps, it's a byte.

Anyway, your issue of loopback will be solved by syncing the cloc
domains.


"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
tnx for your comment, so what should i do? i have tested the following
code
too, but still i have error in receiving packets.
assign RTL_TXE=RTL_RXDV;
assign RTL_TXD=RTL_RXD;

If your receiver gives you a clock, put that on a global clock, work wit

the data in this domain and also feed the transmitter with it. Be carefu

with timing. I would need your schematic diagram to tell more.

tnx in advanced for help :)
Neda Baheri

NP
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
My problem got solved, had to do the timing analysis once again. Although
XST wasn't reporting any timing failures, but I was on boundary, so onc
in
a while I was getting the issue.

As far as your issue is concerned, what you are missing as pointed out by
NP is that you have two clock domains. So, you need to sync these tw
clock
domains. I think your phy is giving you both TXCLK and RXCLK at 25Mhz
for
100Mbps, correct me if i am wrong.

The best thing would be use a buffer at the incoming interface, write the
data to the FIFO on RXCLK and after 4-5 writes, read the packet bytes at
TXCLK.
Also, you do know how the ethernet works, right ? like in 100Mbps yo
have
to deal with a nibble at a time, and in 1000Mbps, it's a byte.

Anyway, your issue of loopback will be solved by syncing the clock
domains.


"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
tnx for your comment, so what should i do? i have tested the followin

code
too, but still i have error in receiving packets.
assign RTL_TXE=RTL_RXDV;
assign RTL_TXD=RTL_RXD;

If your receiver gives you a clock, put that on a global clock, wor
with

the data in this domain and also feed the transmitter with it. B
careful

with timing. I would need your schematic diagram to tell more.

tnx in advanced for help :)
Neda Baheri

NP




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
hi
tnx for your suggestion, i am working on the fpga program as you suggested
but my problem still exist,i used chipscope to debug the problem, the dat
is received fine to fpga but it seemed that the data is not write and rea
back from dual port ram, here is the code. i don't know what's the proble
and how should i proceed? thanks in advanced for help

i read the data received from lan in this process and write in DPRAM
generate a strob to transmit process to start sending data at the fallin
edge of RXDV, and capturing the end of packet transmition for resetin
write address:

always @(posedge RTL_RXCLK)
begin

/// Reading Data from RXD pin and save it in dpram
if(RTL_RXDV)
begin
write_address2 <= write_address2+1;
Ram_Data_In <= RTL_RXD;
Ram_Write_Enable<=1;
end
else
Ram_Write_Enable<=0;

///Set Receive Packet Strob to transmit section
pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
begin
loopback_data<=1;
PacketReceived <= PacketReceived +1;

end
/// reset Receive Packet Strob
if(loopback_data)
begin
DelayCcLpbackData <= DelayCcLpbackData + 1;
if(DelayCcLpbackData>=50)
begin
loopback_data<=0;
DelayCcLpbackData<=0;
end
end

/// capture End ot Trasmission
preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
begin
write_address2<=0;

end
end
//////

always @(posedge RTL_TXCLK )
begin
/// Capture Rising edge of Receive packet Strob generated b
receive process
pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
begin
StartSendingData<=1;
end

// start transmitting data
if(StartSendingData)
begin
read_address2<=read_address2+1;
rgRTL_TXD<=Ram_Data_Out;
rgRTL_TXE <=1;
re_en<=1;
if(read_address2>write_address2)
begin
read_address2<=0;
re_en<=0;
rgRTL_TXE <=0;


End_Sending_Strobe <= 1;
StartSendingData<=0;
end
end

//////////////
if(End_Sending_Strobe)
begin
DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
if(DelayCcResetSendStrobe>=50)
begin
DelayCcResetSendStrobe <= 0;
End_Sending_Strobe <= 0;
end
end

end



duall_ram2 duall_ram2_in2
(
.CLCK_re(RTL_TXCLK),
.CLCK_wr(RTL_RXCLK),
.DIN(Ram_Data_In),
.Re(re_en),
.RE_ADDRESS(read_address2),
.We(Ram_Write_Enable),
.wr_address(write_address2),
.dout(Ram_Data_Out)
);

and the module for DPRAM is :
entity duall_ram2 is
Port ( DIN : in std_logic_vector(3 downto 0);
RE_ADDRESS : in std_logic_vector(10 downto 0);
wr_address :in std_logic_vector(10 downto 0);
CLCK_wr : in std_logic;
CLCK_re : in std_logic;
We : in std_logic;
Re : in std_logic;
dout : out std_logic_vector(3 downto 0));
end duall_ram2 ;

architecture Behavioral of duall_ram2 is
type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
signal rom: my_data;
begin

process (clck_wr)--write
begin
if (clck_wr'event and clck_wr = '0') then
if (we = '1') then
rom(conv_integer(WR_address)) <= din;

end if;
end if;
end process;

process (clck_re)--read
begin
if (clck_re'event and clck_re = '0') then ---e
if (Re = '1') then
dout<=rom(conv_integer(RE_address));
end if;

end if;
end process;

---------------------------------------
Posted through http://www.FPGARelated.com
 
and one thing more, i also used the dual port ram from ISE instances , bu
out put is the same.

tnx in advanced for help

RAMB16_S4_S4 RAMB16_S4_S4_inst
(
// .DOA(), // Port A 4-bit Data Output
.DOB(Ram_Data_Out), // Port B 4-bit Data Output
.ADDRA(write_address2), // Port A 12-bit Address Input
.ADDRB(read_address2), // Port B 12-bit Address Input
.CLKA(GlobalClk), // Port A Clock
.CLKB(GlobalClk), // Port B Clock
.DIA(Ram_Data_In), // Port A 4-bit Data Input
//.DIB(DIB), // Port B 4-bit Data Input
.ENA(1), // Port A RAM Enable Input
.ENB(1), // Port B RAM Enable Input
.SSRA(0), // Port A Synchronous Set/Reset Input
.SSRB(0), // Port B Synchronous Set/Reset Input
.WEA(Ram_Write_Enable), // Port A Write Enable Input
.WEB(0) // Port B Write Enable Input
);


---------------------------------------
Posted through http://www.FPGARelated.com
 
First of all, although not related to your query but in general a goo
practice, you need to sync your signals in the FPGA. Like the signals RX
and RXDV although in sync with the RXCLK, you need to flop them in th
system, then use it wherever you want to.
Now, few things:
1- why aren't you using the RXDV signal as a write signal to DPRAM and RX
as input?

2- Also, what you can do is, you can use a Coregen FIFO in your desig
instead of DPRAM. For DPRAM, you may require a controller, for FIFO yo
won't. So, just to test your logic, you can use FIFO instead. Then star
reading when RXDV goes low.





---------------------------------------
Posted through http://www.FPGARelated.com


hi
tnx for your suggestion, i am working on the fpga program as yo
suggested,
but my problem still exist,i used chipscope to debug the problem, th
data
is received fine to fpga but it seemed that the data is not write an
read
back from dual port ram, here is the code. i don't know what's th
problem
and how should i proceed? thanks in advanced for help

i read the data received from lan in this process and write in DPRAM,
generate a strob to transmit process to start sending data at the falling
edge of RXDV, and capturing the end of packet transmition for reseting
write address:

always @(posedge RTL_RXCLK)
begin

/// Reading Data from RXD pin and save it in dpram
if(RTL_RXDV)
begin
write_address2 <= write_address2+1;
Ram_Data_In <= RTL_RXD;
Ram_Write_Enable<=1;
end
else
Ram_Write_Enable<=0;

///Set Receive Packet Strob to transmit section
pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
begin
loopback_data<=1;
PacketReceived <= PacketReceived +1;

end
/// reset Receive Packet Strob
if(loopback_data)
begin
DelayCcLpbackData <= DelayCcLpbackData + 1;
if(DelayCcLpbackData>=50)
begin
loopback_data<=0;
DelayCcLpbackData<=0;
end
end

/// capture End ot Trasmission
preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
begin
write_address2<=0;

end
end
//////

always @(posedge RTL_TXCLK )
begin
/// Capture Rising edge of Receive packet Strob generated by
receive process
pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
begin
StartSendingData<=1;
end

// start transmitting data
if(StartSendingData)
begin
read_address2<=read_address2+1;
rgRTL_TXD<=Ram_Data_Out;
rgRTL_TXE <=1;
re_en<=1;
if(read_address2>write_address2)
begin
read_address2<=0;
re_en<=0;
rgRTL_TXE <=0;


End_Sending_Strobe <= 1;
StartSendingData<=0;
end
end

//////////////
if(End_Sending_Strobe)
begin
DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
if(DelayCcResetSendStrobe>=50)
begin
DelayCcResetSendStrobe <= 0;
End_Sending_Strobe <= 0;
end
end

end



duall_ram2 duall_ram2_in2
(
.CLCK_re(RTL_TXCLK),
.CLCK_wr(RTL_RXCLK),
.DIN(Ram_Data_In),
.Re(re_en),
.RE_ADDRESS(read_address2),
.We(Ram_Write_Enable),
.wr_address(write_address2),
.dout(Ram_Data_Out)
);

and the module for DPRAM is :
entity duall_ram2 is
Port ( DIN : in std_logic_vector(3 downto 0);
RE_ADDRESS : in std_logic_vector(10 downto 0);
wr_address :in std_logic_vector(10 downto 0);
CLCK_wr : in std_logic;
CLCK_re : in std_logic;
We : in std_logic;
Re : in std_logic;
dout : out std_logic_vector(3 downto 0));
end duall_ram2 ;

architecture Behavioral of duall_ram2 is
type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
signal rom: my_data;
begin

process (clck_wr)--write
begin
if (clck_wr'event and clck_wr = '0') then
if (we = '1') then
rom(conv_integer(WR_address)) <= din;

end if;
end if;
end process;

process (clck_re)--read
begin
if (clck_re'event and clck_re = '0') then ---e
if (Re = '1') then
dout<=rom(conv_integer(RE_address));
end if;

end if;
end process;

---------------------------------------
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Click to expand...
---------------------------------------
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Thank you for your useful comments :), my problem was solved . it was du
to writing clk in dpram, this clk was 100mhz and I expected that the dat
was surely written in memory before the next rxclk which was 25MHZ,
changed writing clk to RXCLK and the problem was solved.
But a question, as it seemed to me that syncing signal are important(caus
my problem was exactly due that) how should I do that??
I don't know how to sync RXD and RXDV?
tnx in advanced for help
Neda Baheri


First of all, although not related to your query but in general a good
practice, you need to sync your signals in the FPGA. Like the signals RXD
and RXDV although in sync with the RXCLK, you need to flop them in the
system, then use it wherever you want to.
Now, few things:
1- why aren't you using the RXDV signal as a write signal to DPRAM an
RXD
as input?

2- Also, what you can do is, you can use a Coregen FIFO in your design
instead of DPRAM. For DPRAM, you may require a controller, for FIFO you
won't. So, just to test your logic, you can use FIFO instead. Then start
reading when RXDV goes low.






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hi
tnx for your suggestion, i am working on the fpga program as you
suggested,
but my problem still exist,i used chipscope to debug the problem, the
data
is received fine to fpga but it seemed that the data is not write and
read
back from dual port ram, here is the code. i don't know what's the
problem
and how should i proceed? thanks in advanced for help

i read the data received from lan in this process and write in DPRAM,
generate a strob to transmit process to start sending data at th
falling
edge of RXDV, and capturing the end of packet transmition for reseting
write address:

always @(posedge RTL_RXCLK)
begin

/// Reading Data from RXD pin and save it in dpram
if(RTL_RXDV)
begin
write_address2 <= write_address2+1;
Ram_Data_In <= RTL_RXD;
Ram_Write_Enable<=1;
end
else
Ram_Write_Enable<=0;

///Set Receive Packet Strob to transmit section
pre_RTL_RXDV <= {pre_RTL_RXDV[0],RTL_RXDV} ;
if( ~pre_RTL_RXDV[0] & pre_RTL_RXDV[1])
begin
loopback_data<=1;
PacketReceived <= PacketReceived +1;

end
/// reset Receive Packet Strob
if(loopback_data)
begin
DelayCcLpbackData <= DelayCcLpbackData + 1;
if(DelayCcLpbackData>=50)
begin
loopback_data<=0;
DelayCcLpbackData<=0;
end
end

/// capture End ot Trasmission
preEnd_SendStrobe <= {preEnd_SendStrobe[0],End_SendStrobe};
if( preEnd_SendStrobe[0] & ~preEnd_SendStrobe[1])
begin
write_address2<=0;

end
end
//////

always @(posedge RTL_TXCLK )
begin
/// Capture Rising edge of Receive packet Strob generated by
receive process
pre_Loopback_data <= {pre_Loopback_data[0],loopback_data};
if(pre_Loopback_data[0] & ~pre_Loopback_data[1])
begin
StartSendingData<=1;
end

// start transmitting data
if(StartSendingData)
begin
read_address2<=read_address2+1;
rgRTL_TXD<=Ram_Data_Out;
rgRTL_TXE <=1;
re_en<=1;
if(read_address2>write_address2)
begin
read_address2<=0;
re_en<=0;
rgRTL_TXE <=0;


End_Sending_Strobe <= 1;
StartSendingData<=0;
end
end

//////////////
if(End_Sending_Strobe)
begin
DelayCcResetSendStrobe<=DelayCcResetSendStrobe+1;
if(DelayCcResetSendStrobe>=50)
begin
DelayCcResetSendStrobe <= 0;
End_Sending_Strobe <= 0;
end
end

end



duall_ram2 duall_ram2_in2
(
.CLCK_re(RTL_TXCLK),
.CLCK_wr(RTL_RXCLK),
.DIN(Ram_Data_In),
.Re(re_en),
.RE_ADDRESS(read_address2),
.We(Ram_Write_Enable),
.wr_address(write_address2),
.dout(Ram_Data_Out)
);

and the module for DPRAM is :
entity duall_ram2 is
Port ( DIN : in std_logic_vector(3 downto 0);
RE_ADDRESS : in std_logic_vector(10 downto 0);
wr_address :in std_logic_vector(10 downto 0);
CLCK_wr : in std_logic;
CLCK_re : in std_logic;
We : in std_logic;
Re : in std_logic;
dout : out std_logic_vector(3 downto 0));
end duall_ram2 ;

architecture Behavioral of duall_ram2 is
type my_data is array (0 to 2045)of std_logic_vector(3 downto 0) ;
signal rom: my_data;
begin

process (clck_wr)--write
begin
if (clck_wr'event and clck_wr = '0') then
if (we = '1') then
rom(conv_integer(WR_address)) <= din;

end if;
end if;
end process;

process (clck_re)--read
begin
if (clck_re'event and clck_re = '0') then ---e
if (Re = '1') then
dout<=rom(conv_integer(RE_address));
end if;

end if;
end process;

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