GHDL and Xilinx

Guest
Hello everyone,

I'm trying to simulate some Xilinx VHDL design with GHDL... with poor
results... I made a simple project as a schematic, with the RAM16x1d
block (it's a Xilinx IP core). With Xilinx ise i generate the vhf file
for the vhdl simulation. So i have two files:

Toplevel.vhf
Topleveltest.vhd (a simple testbench)

Here is what I do:

1) I import the unisim library with "GHDL -i --work=unisim C:/
Xilinx91i/vhdl/src/unisims/*.vhd

2) I import project files:
ghdl -i --work=work toplevel.vhf topleveltest.vhf

3) I run the testbench:
ghdl -r toplevel_tb --stop-time=200ns

Doing these three steps i get an error: GHDL isn't able to bind the
components with the unisim entities. So I add a configuration for each
component in toplevel.vhf:

for all : RAMB16xD1 use entity unisim.RAM16xD1;
for all : IBUF use entity unisim.IBUF;
for all : OBUF use entity unisim.OBUF;

I repeat steps 2 and 3 with these lines added, but now i get a new
error:

toplevel.vhf:103:40: entity "ram16x1d_1" is obsoleted by package
"vpkg"
toplevel.vhf:103:26: entity "ram16x1d_1" is obsolete

Package VPKG is part of the unisim library. What does the error mean?
Any clue about possible solutions?
My objective is to find out whether it's possible to perform timing
simulations with GHDL+ISE... Anyone is using it for this purpose?
 
lelesa@inwind.it writes:

1) I import the unisim library with "GHDL -i --work=unisim C:/
Xilinx91i/vhdl/src/unisims/*.vhd
Click to expand...
AFAIR the order is important. Don't use *.vhd, but vcomp, vpkg, vital and smodel
in that order.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
 
Ok, thanks, that seems to work...

but now, when i try to run the testbench, i get this error:

ghdl: cannot load package "vcomponents"

When i try with "ghdl -d --work=unisim" i can see the package in the
list... Any clue?

Georg Acher ha scritto:

lelesa@inwind.it writes:

1) I import the unisim library with "GHDL -i --work=unisim C:/
Xilinx91i/vhdl/src/unisims/*.vhd

AFAIR the order is important. Don't use *.vhd, but vcomp, vpkg, vital and smodel
in that order.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Click to expand...
 
In article <1181588337.662073.184180@q66g2000hsg.googlegroups.com>,
lelesa@inwind.it writes:
|> Ok, thanks, that seems to work...
|>
|> but now, when i try to run the testbench, i get this error:
|>
|> ghdl: cannot load package "vcomponents"
|>
|> When i try with "ghdl -d --work=unisim" i can see the package in the
|> list... Any clue?

Hm, this is the way it works for me:

Create a directory "unisim" and put all the Xilinx-unisim*-files in it. The test
files are above this folder.

Analyze the unisim-stuff with "ghdl -a --work=unisim --ieee=synopsys
-fexplicit" in the mentioned order, so the unisim-*.o-files are in unisim/

Analyze the test files with "ghdl -a -Punisim".

Elaborate with "ghdl -e -Punisim --ieee=synopsys -fexplicit"

After that, a tiny little executable (about 21MB) comes out and runs fine.

I'm using ghdl-0.25 and slightly patched unisims from ISE 8.2.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
 
On 11 Giu, 23:15, a...@in.tum.de (Georg Acher) wrote:
In article <1181588337.662073.184...@q66g2000hsg.googlegroups.com>, lel...@inwind.it writes:

|> Ok, thanks, that seems to work...
|
|> but now, when i try to run the testbench, i get this error:
|
|> ghdl: cannot load package "vcomponents"
|
|> When i try with "ghdl -d --work=unisim" i can see the package in the
|> list... Any clue?

Hm, this is the way it works for me:

Create a directory "unisim" and put all the Xilinx-unisim*-files in it. The test
files are above this folder.

Analyze the unisim-stuff with "ghdl -a --work=unisim --ieee=synopsys
-fexplicit" in the mentioned order, so the unisim-*.o-files are in unisim/

Analyze the test files with "ghdl -a -Punisim".

Elaborate with "ghdl -e -Punisim --ieee=synopsys -fexplicit"

After that, a tiny little executable (about 21MB) comes out and runs fine.

I'm using ghdl-0.25 and slightly patched unisims from ISE 8.2.

--
Georg Acher, a...@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Click to expand...
Ok, I guess the problem is i'm using win32 build of GHDL...
 
Georg Acher wrote:

In article <1181588337.662073.184180@q66g2000hsg.googlegroups.com>,
lelesa@inwind.it writes:
|> Ok, thanks, that seems to work...
|
|> but now, when i try to run the testbench, i get this error:
|
|> ghdl: cannot load package "vcomponents"
|
|> When i try with "ghdl -d --work=unisim" i can see the package in the
|> list... Any clue?

Hm, this is the way it works for me:

Create a directory "unisim" and put all the Xilinx-unisim*-files in it. The test
files are above this folder.

Analyze the unisim-stuff with "ghdl -a --work=unisim --ieee=synopsys
-fexplicit" in the mentioned order, so the unisim-*.o-files are in unisim/

Analyze the test files with "ghdl -a -Punisim".

Elaborate with "ghdl -e -Punisim --ieee=synopsys -fexplicit"

After that, a tiny little executable (about 21MB) comes out and runs fine.

I'm using ghdl-0.25 and slightly patched unisims from ISE 8.2.
Click to expand...
I'm also interested in this subject. And today I tried this out,
unfortunately with no luck. When I compile (analyze) unisim_VITAL.vhd I get
the following errors:

unisim/unisim_VITAL.vhd:175819:57: variable "write_a_write_b" is not visible here
unisim/unisim_VITAL.vhd:175820:57: variable "read_a_write_b" is not visible here
unisim/unisim_VITAL.vhd:175821:57: variable "write_a_read_b" is not visible here
unisim/unisim_VITAL.vhd:175822:57: variable "write_b_write_a" is not visible here
unisim/unisim_VITAL.vhd:175823:57: variable "read_b_write_a" is not visible here
unisim/unisim_VITAL.vhd:175824:57: variable "write_b_read_a" is not visible here

BTW. This is with the files from the 9.1i release, but the 7.1i release give the same
errors.

I'm wondering if you modified these files to solve this problem, and if so, what
changes did you make?

Kind regards, Kees Bakker
 
In article <50be.467a8e06.7f74f@altium.nl>,
Kees Bakker <spam@altium.nl> writes:

|> I'm also interested in this subject. And today I tried this out,
|> unfortunately with no luck. When I compile (analyze) unisim_VITAL.vhd I get
|> the following errors:
|>
|> unisim/unisim_VITAL.vhd:175819:57: variable "write_a_write_b" is not visible here
|> unisim/unisim_VITAL.vhd:175820:57: variable "read_a_write_b" is not visible here
|> unisim/unisim_VITAL.vhd:175821:57: variable "write_a_read_b" is not visible here
|> unisim/unisim_VITAL.vhd:175822:57: variable "write_b_write_a" is not visible here
|> unisim/unisim_VITAL.vhd:175823:57: variable "read_b_write_a" is not visible here
|> unisim/unisim_VITAL.vhd:175824:57: variable "write_b_read_a" is not visible here
|>
|> BTW. This is with the files from the 9.1i release, but the 7.1i release give
|> the same errors.
|>
|> I'm wondering if you modified these files to solve this problem, and if so,
|> what changes did you make?

Simply comment out the variable lines with the errors. They occur in two places.

I don't understand their need anyway. Assigning the enum value to a variable of
the *same name* and *same type* sounds quite fishy to me. Maybe it's accidently
legal VHDL, but it looks more like a quick hack workaround for some faulty
simulator.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
 
Georg Acher wrote:

In article <50be.467a8e06.7f74f@altium.nl>,
Kees Bakker <spam@altium.nl> writes:

|> I'm also interested in this subject. And today I tried this out,
|> unfortunately with no luck. When I compile (analyze) unisim_VITAL.vhd I get
|> the following errors:
|
|> unisim/unisim_VITAL.vhd:175819:57: variable "write_a_write_b" is not visible here
|> unisim/unisim_VITAL.vhd:175820:57: variable "read_a_write_b" is not visible here
|> unisim/unisim_VITAL.vhd:175821:57: variable "write_a_read_b" is not visible here
|> unisim/unisim_VITAL.vhd:175822:57: variable "write_b_write_a" is not visible here
|> unisim/unisim_VITAL.vhd:175823:57: variable "read_b_write_a" is not visible here
|> unisim/unisim_VITAL.vhd:175824:57: variable "write_b_read_a" is not visible here
|
|> BTW. This is with the files from the 9.1i release, but the 7.1i release give
|> the same errors.
|
|> I'm wondering if you modified these files to solve this problem, and if so,
|> what changes did you make?

Simply comment out the variable lines with the errors. They occur in two places.

I don't understand their need anyway. Assigning the enum value to a variable of
the *same name* and *same type* sounds quite fishy to me. Maybe it's accidently
legal VHDL, but it looks more like a quick hack workaround for some faulty
simulator.
Click to expand...
Hah! That's it. Thanks.
--
Kees
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top