getting wire or reg input value from commandline in verilog?

P

priya

Guest
Hi,

I want to get the wire or reg input value from commandline?
How is it possible in verilog ?

need to pass the values for reg or wire in the run time (not a compile
time)......



Regards,

Priya
 
priya wrote:
I want to get the wire or reg input value from commandline?
How is it possible in verilog ?

need to pass the values for reg or wire in the run time (not a compile
time)......
At least in Modelsim that is possible with -g/-G switches.
For example vsim '-G/my/hierarchy/MEMORYFILE="memimage.dat"' lib.design

--Kim
 
Thanks...
I am using Icarus Verilog Simulator .....

could u plz explain me little bit more?



Regards,
Priya
 
Hi Kim,
IIRC, this is for overriding parameter/generics from command line
and NOT for input/output values. One needs to use the TCL interface in
Modelsim.

Regards
Ajeetha
www.noveldv.com
 
Priya,
What you are looking for is known as "command line interface" to
a HDL simulator. I know most of today's commerical tools have TCL
interface that can do precisely what you've asked for.

With Icarus - guess not (yet?) - infact that was one of the student
projects that we proposed in our noveldv.com page, but no takers yet
:)-

In your case, you need to use VPI along with some custom C routine to
take input value from STDIN and send it to DUT via vpi_put_value

Does that help?
Ajeetha
www.noveldv.com
 
Take a look at $test$plusargs and $value$plusargs routines.

I suspect using them you can then force regs to the desired value

John Providenza
 
Ajeetha wrote:
Priya,
What you are looking for is known as "command line interface" to
a HDL simulator. I know most of today's commerical tools have TCL
interface that can do precisely what you've asked for.

With Icarus - guess not (yet?) - infact that was one of the student
projects that we proposed in our noveldv.com page, but no takers yet
:)-

In your case, you need to use VPI along with some custom C routine to
take input value from STDIN and send it to DUT via vpi_put_value
Icarus Verilog supports $test$plusargs and $value$plusargs. This will
allow one to pass argument flags and values to the run-time of a simulation.
 

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