Getting started with partial reconfiguration

[Richard]

Hi,

I wanna get started to design architectures with partially
reconfiguarable modules. I am using a Virtex-5, according
to the manual this board now also allows to dyanmically
change the clock using the DRP port. The way to implement
partially reconfigurable logic blocks seems to be described
in this document:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug702.pdf

I assume this is the state-of-the-art since it has been recently
purchased. I am wondering if somebody has maybe additional ressources
that are helpful to get started with this topic. In particular a very
simple would be very helpful to get a deeper insight how it works.

The ultimate goal is then to have a design the partially changes
it reconfiguration depending on the input. Silly question: From where
will the partial modules be loaded? From Flash or are the somehow
requested over the JTAG interface when they are required?

Many thanks for your help,
Rich

 

[Gabor]

On Jul 27, 8:43 pm, Richard <Richard.Gran...@hotmail.com> wrote:

Hi,

I wanna get started to design architectures with partially
reconfiguarable modules. I am using a Virtex-5, according
to the manual this board now also allows to dyanmically
change the clock using the DRP port. The way to implement
partially reconfigurable logic blocks seems to be described
in this document:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug7...

I assume this is the state-of-the-art since it has been recently
purchased. I am wondering if somebody has maybe additional ressources
that are helpful to get started with this topic. In particular a very
simple would be very helpful to get a deeper insight how it works.

The ultimate goal is then to have a design the partially changes
it reconfiguration depending on the input. Silly question: From where
will the partial modules be loaded? From Flash or are the somehow
requested over the JTAG interface when they are required?

Many thanks for your help,
Rich

Don't confuse "Dynamic" and "Partial" configuration. They mean two
different
things (at least to Xilinx). The DRP is a bus that lets you program
the DCM
and other hard IP blocks inside the V5 from your other fabric logic.

Partial reconfiguration uses the JTAG or parallel configuration
ports. This
is more like configuring the entire part but it only affects a portion
of the
chip. The hardest part of achieving this is partitioning the design
so
that a portion of the chip can be re-used without breaking the
remaining
running design.

HTH,
Gabor

 

[Kate Kelley]

The other place you can ask question and get more information is the H
Xilinx Forum.

http://forums.xilinx.com/t5/Hierarchical-Design/bd-p/Hier_Des

There is also a new PR Video here:

http://www.xilinx.com/products/design_resources/design_tool/resources/index.htm

I am not a PR expert so I can't answer your question but I do think ther
are several different ways to get the new configuration loaded into th
FPGA device.

Kate

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