Get Warning message ".. unsafe behavior" WHY?!

[benn]

If the following looks like a hack, it's because I'm totally new to
this.. I welcome any and all suggestions on how it could be improved,
or why it's dangerous. The compiler gives 2 warnings about "unsafe
behavior" for both the MUX_SEL_REG and the ACTIVE registers!

I have no idea why it's unsafe, but it probably explains why the code
doesn't work! In *THEORY* it should work like the waveforms:
http://i39.tinypic.com/121y87q.jpg (top wave is the timeout scenario)

// time(s) = COUNTER / 200e6 (100Mhz clock)
`define TIME_14us 16'd2800
`define TIME_1p5us 16'd300
`define RESPONSE_TOGGLE_TIME `TIME_1p5us
`define TIMEOUT_TIME `TIME_14us

module MUX_TOGGLE(input LINE_1, input clk, input LINE_2, output
MUX_SEL);
reg [15:0]stableCounter;
reg ACTIVE;
reg MUX_SEL_REG;

assign MUX_SEL = MUX_SEL_REG;

always @(LINE_1, LINE_2, clk)
if ( ( ~LINE_1 ) && (~LINE_2) )
begin
stableCounter = stableCounter + 1'b1;
if (stableCounter >= `TIMEOUT_TIME)
begin
MUX_SEL_REG = 1'b0; //LINE_1 ACTIVE
stableCounter = `TIMEOUT_TIME;
end
else if ((stableCounter >= `RESPONSE_TOGGLE_TIME) && ( ACTIVE ) )
begin
MUX_SEL_REG = MUX_SEL_REG ^ 1'b1; //TOGGLE BUS
ACTIVE = 1'b0;
end
end
else if ( LINE_1 )
begin
ACTIVE = 1'b1;
stableCounter = 16'd0;
MUX_SEL_REG = 1'b0; //LINE_1 ACTIVE
end
else if ( LINE_2 )
begin
ACTIVE = 1'b1;
stableCounter = 16'd0;
MUX_SEL_REG = 1'b1; //LINE_2 ACTIVE
end
endmodule

When I try the code, however, the counter seems to be counting all
over the place!

The basic idea is that this module takes two wires, and if it detects
activity in LINE_1, it waits till its finished (and a bit more) and
then toggles MUX_SEL. It then waits for activity on LINE_2 to finish
before switching back MUX_SEL. And in the case where there's no
activity on LINE_2, it times out and also reverts MUX_SEL.

Suggestions?

 

[Jason Zheng]

On Wed, 28 Jan 2009 15:21:49 -0800 (PST)
benn <benn686@hotmail.com> wrote:

When I try the code, however, the counter seems to be counting all
over the place!

The basic idea is that this module takes two wires, and if it detects
activity in LINE_1, it waits till its finished (and a bit more) and
then toggles MUX_SEL. It then waits for activity on LINE_2 to finish
before switching back MUX_SEL. And in the case where there's no
activity on LINE_2, it times out and also reverts MUX_SEL.

Suggestions?

My honest opinion: don't try to implement hw as if you were
implementing sw. There are so many things wrong with your code that I'd
suggest you start over. First you need to do is to think and draw a
diagram of what you are trying to design. Draw the diagram with
counters, comparators, and flip-flops. If you can't draw the diagram
and convince yourself that it should work, then you shouldn't be
designing hw.

I might sound harsh, but I'm not trying to make fun of you. But really,
where/who did you learn Verilog from?