genvar part-select expression

N

nanako

Guest
Is genvar part-select expression legal?

genvar i;
generate
for(i = 0; i < 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate

It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.
 
On 02/10/2012 02:35 PM, Mark Curry wrote:
In article <31fc4768-57a6-4249-83ab-ac8e36381167@og8g2000pbb.googlegroups.com>,
nanako <nanako.mizuki@gmail.com> wrote:
Is genvar part-select expression legal?

genvar i;
generate
for(i = 0; i < 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate

It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.


My two cents - remove all doubt.

for(i = 0; i < 8; i = i + 1)begin : gen
wire [2:0] foo = i;
assign q2_t[ foo ] = ...

Parameters (and genvars) are kind of "fuzzy" with respect to size. I'm sure
the LRM addresses just about every corner of this. But for me, if there's any
question in your mind, just fix it now such that there's no doubt.
Parameters can be explicitly sized:

parameter [2:0] foo = 5;

No ambiguity WRT size there, and yes you can bin/part select parameters
and local params. Genvars are indeed a bit more fuzzy, because there is
no way to specify the size of a genvar. (Interesting oversight. I'll
have to look into that.) In that case, if you really do want a size
for your genvar, then make a localparam variation like this:

genvar i;
for (i = 0 ; i < 8 ; i = i+1) begin : gen
localparam [2:0] i_sized = i;
assign q2_t[i_sized] = ...
end


--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
In article <31fc4768-57a6-4249-83ab-ac8e36381167@og8g2000pbb.googlegroups.com>,
nanako <nanako.mizuki@gmail.com> wrote:
Is genvar part-select expression legal?

genvar i;
generate
for(i = 0; i < 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate

It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.
My two cents - remove all doubt.

for(i = 0; i < 8; i = i + 1)begin : gen
wire [2:0] foo = i;
assign q2_t[ foo ] = ...

Parameters (and genvars) are kind of "fuzzy" with respect to size. I'm sure
the LRM addresses just about every corner of this. But for me, if there's any
question in your mind, just fix it now such that there's no doubt.

--Mark
 
On 2/10/2012 3:16 PM, Stephen Williams wrote:
On 02/10/2012 02:35 PM, Mark Curry wrote:
In article<31fc4768-57a6-4249-83ab-ac8e36381167@og8g2000pbb.googlegroups.com>,
nanako<nanako.mizuki@gmail.com> wrote:
Is genvar part-select expression legal?

genvar i;
generate
for(i = 0; i< 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate

It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.


My two cents - remove all doubt.

for(i = 0; i< 8; i = i + 1)begin : gen
wire [2:0] foo = i;
assign q2_t[ foo ] = ...

Parameters (and genvars) are kind of "fuzzy" with respect to size. I'm sure
the LRM addresses just about every corner of this. But for me, if there's any
question in your mind, just fix it now such that there's no doubt.

Parameters can be explicitly sized:

parameter [2:0] foo = 5;

No ambiguity WRT size there, and yes you can bin/part select parameters
and local params. Genvars are indeed a bit more fuzzy, because there is
no way to specify the size of a genvar. (Interesting oversight. I'll
have to look into that.) In that case, if you really do want a size
for your genvar, then make a localparam variation like this:

genvar i;
for (i = 0 ; i< 8 ; i = i+1) begin : gen
localparam [2:0] i_sized = i;
assign q2_t[i_sized] = ...
end
1364-2005 section 12.4.1 implies that a genvar is an integer that is
only used during elaboration inside a generate loop scheme. From this, I
would assume all the usual integer rules apply to a genvar. I'm assuming
integer in this context relates to the typical Verilog integer variable
not a more general and not explicitly defined integer variable.

Cary
 

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