N
nanako
Guest
Is genvar part-select expression legal?
genvar i;
generate
for(i = 0; i < 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate
It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.
genvar i;
generate
for(i = 0; i < 8; i = i + 1)begin : gen
assign q2_t[i[2:0]] = (counter == i[2:0] || ((counter + 3'h1) ==
i[2:0]))? 1'b1 : 1'b0;
end
endgenerate
It seems to work in ModelSim.
However genvar index property(bit width) is not explicitly defined in
LRM.