generics in TB

[valentin tihomirov]

My TB submits inputs to a DUT and saves the outputs. The widths of input and
output ports of the DUT are arbitrary. Is it possible to create such a TB
that can deal with arbitrary number of inputs and outputs in DUT? I have no
ideas about how should VHDL code look like. For example, the genreal
interface of DUT is:

entity CUS is -- circuit unter simulation interface
generic (
I_WIDTH : Integer;
O_WIDTH : Integer
);
port (
INPUTS: STD_LOGIC_VECTOR (I_WIDTH-1 downto 0);
OUTPUTS: STD_LOGIC_VECTOR (O_WIDTH-1 downto 0)
);
end CUS;



and particular device, let's say a 1-bit inverter, conforming to this
interface:

architecture INV of CUS is
begin
-- specify I_WIDTH = O_WIDTH := 1 somehow
OUTPUTS <= not INPUTS;
end INV;


I need to specify width of inputs and outputs = constant 1 for particular
circuit implementing CUS interface. The same constant should be passed to TB
during instantiation of CUS.

 

[Jonathan Bromley]

"valentin tihomirov" <valentinNOSPAM@abelectron.com> wrote
in message news:brqarj$6cc7v$1@ID-212430.news.uni-berlin.de...

My TB submits inputs to a DUT and saves the outputs. The widths of input
and
output ports of the DUT are arbitrary. Is it possible to create such a TB
that can deal with arbitrary number of inputs and outputs in DUT?
[...]
I need to specify width of inputs and outputs = constant 1 for particular
circuit implementing CUS interface. The same constant should be passed to
TB
during instantiation of CUS.

hi Valentin,

There are quite a few possible approaches to your problem, but
first you must note that VHDL does NOT permit a lower-level
(child) module instance to control constant or generic values
in its parent. Instead, the parent must "push" values down
into its child instances, typically through a generic map.

You can set the port sizes on your CUS from the test bench,
as I guess you know:

entity TB is end;
architecture A of TB is
constant WIDTH: positive := 5;
signal A, B: std_logic_vector(WIDTH-1 downto 0);
...
begin
DUT: CUS
generic map (I_WIDTH => WIDTH, O_WIDTH => WIDTH)
port map (INPUTS => A, OUTPUTS => B);
...
end;

The question, of course, is how to configure the constant
WIDTH in the top-level test bench.

Here are a few suggestions:

(1) Make the constant a deferred constant in a package.
Now you can change it simply by re-compiling the
package body.
(2) Make the constant a generic of entity TB. Most
simulators will allow you to modify such top-level
generics at the time you elaborate or load the
simulation.
(3) Make the constant a generic of entity TB, then
build a very simple wrapper around it so that you
can use a configuration to set the generic's value.

Here's a sketch of how (3) might work:

entity TB is
generic (WIDTH: positive := 5);
end;
architecture A of TB is
...
begin
...
end;

entity TB_WRAPPER is end;
architecture SIMPLE of TB_WRAPPER is
component TB end component;
begin
The_Test_Bench: TB;
end;

Now you can use a configuration to set up the generic
value in TB:

configuration C1 of TB_WRAPPER is
for SIMPLE
for The_Test_Bench: TB
use entity TB(A)
generic map (WIDTH => 1);
end for;
end for;
end;

and you can easily create many different configurations
with different values of top-level generic.

Hope this helps a little
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[valentin tihomirov]

Thanks for the help. You have shown how to pass a constant to TB (using
package) and how to assert the contant to generic param of TB. But how do I
specify the constant? This should be done in implementing architecture. As
it was shown in my example, DUT's interface is the most generic ever
possibe, it allows for any number of inputs and outputs per circuit. The
task is to specify concrete number of IOs in implementing architecture.

Let's implement AND2 element, for example. It has 2 inputs and 1 output.
Interface is predefined, widths are generic:

entity GENERIC_INTERFACE is
generic (
I_WIDTH : Integer;
O_WIDTH : Integer
);
port (
I: bit_vector (I_WIDTH-1 downto 0);
O: bit_vector (O_WIDTH-1 downto 0)
);
end GENERIC_INTERFACE;


The following architecture will not compile until I specify widths. How do
I?

architecture AND2 of GENERIC_INTERFACE is
begin
O(0) <= I(0) and I(1);
end AND2;

 

[Jonathan Bromley]

"valentin tihomirov" <valentinNOSPAM@abelectron.com> wrote in
message news:brrva0$617pi$1@ID-212430.news.uni-berlin.de...

Thanks for the help. You have shown how to pass a constant to TB (using
package) and how to assert the contant to generic param of TB. But how do
I
specify the constant? .

Sorry, I don't understand what you mean by "This should be done
in implementing architecture". I think I showed you how to set the
generics from the architecture of the test bench. You can't set
an entity's generics from within its own architecture.

it was shown in my example, DUT's interface is the most generic ever
possibe, it allows for any number of inputs and outputs per circuit. The
task is to specify concrete number of IOs in implementing architecture.

Do you mean "in the architecture that instantiates the DUT"?

Let's implement AND2 element, for example. It has 2 inputs and 1 output.
Interface is predefined, widths are generic:

entity GENERIC_INTERFACE is
generic (
I_WIDTH : Integer;
O_WIDTH : Integer
);
port (
I: bit_vector (I_WIDTH-1 downto 0);
O: bit_vector (O_WIDTH-1 downto 0)
~~~~~~~ I guess you mean O: OUT bit_vector...
);
end GENERIC_INTERFACE;

The following architecture will not compile until I specify widths

architecture AND2 of GENERIC_INTERFACE is
begin
O(0) <= I(0) and I(1);
end AND2;

No, this is not true. This architecture compiles just fine,
exactly as it is, with nothing else specified.

Of course, if you set I_WIDTH = 1, then the reference to I(1)
will cause an index range error. This will be detected either
at elaboration time, or possibly at run time. The compiler
cannot detect it, precisely because the compiler has no idea
what the value of I_WIDTH will be when this entity is instantiated.

In your test bench, what is the difficulty with...

entity TB is end;
architecture T of TB is
constant I_BITS: positive := 2;
constant O_BITS: positive := 1;
signal I: bit_vector (I_BITS-1 downto 0);
signal O: bit_vector (O_BITS-1 downto 0);
component GENERIC_INTERFACE
... -- matching the entity declaration
end component;
begin
DUT: GENERIC_INTERFACE
generic map (I_WIDTH => I_BITS, O_WIDTH => O_BITS)
port map (I=>I, O=>O);
StimulusGenerator: process
...
end process;
end;

??

 

[valentin tihomirov]

OK, thanks. Seems I have to define global constants in a package, assert
them in DUT's architecture and use in TB. This way I get a universal TB
capable simulating any circuit without changing source code of TB (stimuls
will be loaded from an external source). Thank you a lot. This is needed for
HW emilator of circuits.