generic std_logic_vector & range

[KCL]

Hi

Is it possible to declare a std_logic_vector of size that is log2(A) with A
a generic??
I was thinking of doing something like a range signal but doesn't work, does
anyoneone have any idea without using integer/natural signal??

Thanks

Alexis


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ztest is
generic(
A : integer :=132
);
port(
rst : in std_logic;
clk : in std_logic;
data_out : out std_logic_vector( range A downto 0 )
);
end ztest;

architecture Behavioral of ztest is
signal cpt: std_logic_vector range (A downto 0);
signal
begin

process (clk)
begin
if rising_edge(clk) then
if rst ='1' then
cpt <= (others=>'0');
else
if unsigned(cpt)=(A) then
cpt <= (others=>'0');
else
cpt <= std_logic_vector(unsigned(cpt)+1);
end if;
end if;
end if
end process;

data_out <= cpt;

end Behavioral;