Generic Parameters in top-level file

A

ALuPin

Guest
Hi newsgroup users,

I have a question concerning generic parameters which I have used for my
component. This component is instantiated in a top level file
as follows. The buses which are connected to the component have a
defined bus width.

When compiling I get the following error message:
Error: VHDL Association List error at zbt_ctrl_top.vhd(97):
actual parameter assigned to formal parameter asize but formal parameter
is not declared.

What is the problem?

Thank you for your help.

--------------------------------------------------------

signal addr_adv_ld_n_reg : STD_LOGIC;
signal addr_reg : STD_LOGIC_VECTOR(17 downto 0);
signal dm_reg : STD_LOGIC_VECTOR(3 downto 0);
signal rd_wr_n_reg : STD_LOGIC;

BEGIN

b2v_ADDR_CTRL_OUT1 : addr_ctrl_out
GENERIC MAP(ASIZE => 18,BWSIZE => 4)
PORT MAP(Clk => CLK,
Reset => RESET,
Lb_rw_n => rd_wr_n_reg,
Lb_adv_ld_n => addr_adv_ld_n_reg,
Lb_addr => addr_reg,
Lb_bw => dm_reg,
Ram_rw_n => RW_N,
Ram_adv_ld_n => ADV_LD_N,
Ram_addr => SA,
Ram_bw_n => BW_N);
 
Hi ALuPin

Could you transmit us the prototype/component declaration.

Thanks,
JaI

ALuPin wrote:

Hi newsgroup users,

I have a question concerning generic parameters which I have used for my
component. This component is instantiated in a top level file
as follows. The buses which are connected to the component have a
defined bus width.

When compiling I get the following error message:
Error: VHDL Association List error at zbt_ctrl_top.vhd(97):
actual parameter assigned to formal parameter asize but formal parameter
is not declared.

What is the problem?

Thank you for your help.

--------------------------------------------------------

signal addr_adv_ld_n_reg : STD_LOGIC;
signal addr_reg : STD_LOGIC_VECTOR(17 downto 0);
signal dm_reg : STD_LOGIC_VECTOR(3 downto 0);
signal rd_wr_n_reg : STD_LOGIC;

BEGIN

b2v_ADDR_CTRL_OUT1 : addr_ctrl_out
GENERIC MAP(ASIZE => 18,BWSIZE => 4)
PORT MAP(Clk => CLK,
Reset => RESET,
Lb_rw_n => rd_wr_n_reg,
Lb_adv_ld_n => addr_adv_ld_n_reg,
Lb_addr => addr_reg,
Lb_bw => dm_reg,
Ram_rw_n => RW_N,
Ram_adv_ld_n => ADV_LD_N,
Ram_addr => SA,
Ram_bw_n => BW_N);
Click to expand...
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY zbt_ctrl_top IS
port
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RD_WR_N : IN STD_LOGIC;
ADDR_ADV_LD_N : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(17 downto 0);
DATA_IN : IN STD_LOGIC_VECTOR(17 downto 0);
DM : IN STD_LOGIC_VECTOR(3 downto 0);
DQ : INOUT STD_LOGIC_VECTOR(17 downto 0);
RW_N : OUT STD_LOGIC;
ADV_LD_N : OUT STD_LOGIC;
BW_N : OUT STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(17 downto 0);
SA : OUT STD_LOGIC_VECTOR(17 downto 0)
);
END zbt_ctrl_top;

ARCHITECTURE bdf_type OF zbt_ctrl_top IS

component addr_ctrl_out
PORT(Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Lb_rw_n : IN STD_LOGIC;
Lb_adv_ld_n : IN STD_LOGIC;
Lb_addr : IN STD_LOGIC_VECTOR(17 downto 0);
Lb_bw : IN STD_LOGIC_VECTOR(3 downto 0);
Ram_rw_n : OUT STD_LOGIC;
Ram_adv_ld_n : OUT STD_LOGIC;
Ram_addr : OUT STD_LOGIC_VECTOR(17 downto 0);
Ram_bw_n : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end component;

component data_inout
PORT(Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Ctrl_in_rw_n : IN STD_LOGIC_VECTOR(17 downto 0);
Data_in : IN STD_LOGIC_VECTOR(17 downto 0);
Dq : INOUT STD_LOGIC_VECTOR(17 downto 0);
Read_data : OUT STD_LOGIC_VECTOR(17 downto 0)
);
end component;

component pipe_delay
PORT(Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Lb_rw_n : IN STD_LOGIC;
Lb_data_in : IN STD_LOGIC_VECTOR(17 downto 0);
Ram_data_out : IN STD_LOGIC_VECTOR(17 downto 0);
Delay_data_in : OUT STD_LOGIC_VECTOR(17 downto 0);
Delay_rw_n : OUT STD_LOGIC_VECTOR(17 downto 0);
Lb_data_out : OUT STD_LOGIC_VECTOR(17 downto 0)
);
end component;

component pipe_stage
PORT(Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Rd_wr_n : IN STD_LOGIC;
Addr_adv_ld_n : IN STD_LOGIC;
Addr : IN STD_LOGIC_VECTOR(17 downto 0);
Data_in : IN STD_LOGIC_VECTOR(17 downto 0);
Data_out : IN STD_LOGIC_VECTOR(17 downto 0);
Dm : IN STD_LOGIC_VECTOR(3 downto 0);
Rd_wr_n_reg : OUT STD_LOGIC;
Addr_adv_ld_n_reg : OUT STD_LOGIC;
Addr_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
Data_in_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
Data_out_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
Dm_reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end component;

signal addr_adv_ld_n_reg : STD_LOGIC;
signal addr_reg : STD_LOGIC_VECTOR(17 downto 0);
signal data_in_reg : STD_LOGIC_VECTOR(17 downto 0);
signal delay_data_in : STD_LOGIC_VECTOR(17 downto 0);
signal delay_rw_n : STD_LOGIC_VECTOR(17 downto 0);
signal dm_reg : STD_LOGIC_VECTOR(3 downto 0);
signal lb_data_out : STD_LOGIC_VECTOR(17 downto 0);
signal rd_wr_n_reg : STD_LOGIC;
signal read_data : STD_LOGIC_VECTOR(17 downto 0);


BEGIN



b2v_ADDR_CTRL_OUT1 : addr_ctrl_out
GENERIC MAP(ASIZE => 18,BWSIZE => 4)
PORT MAP(Clk => CLK,
Reset => RESET,
Lb_rw_n => rd_wr_n_reg,
Lb_adv_ld_n => addr_adv_ld_n_reg,
Lb_addr => addr_reg,
Lb_bw => dm_reg,
Ram_rw_n => RW_N,
Ram_adv_ld_n => ADV_LD_N,
Ram_addr => SA,
Ram_bw_n => BW_N);

b2v_DATA_INOUT1 : data_inout
GENERIC MAP(BWSIZE => 4,DSIZE => 18)
PORT MAP(Clk => CLK,
Reset => RESET,
Ctrl_in_rw_n => delay_rw_n,
Data_in => delay_data_in,
Dq => DQ,
Read_data => read_data);

b2v_inst2 : pipe_delay
GENERIC MAP(BWSIZE => 4,DSIZE => 18,FLOWTHROUGH => 0)
PORT MAP(Clk => CLK,
Reset => RESET,
Lb_rw_n => rd_wr_n_reg,
Lb_data_in => data_in_reg,
Ram_data_out => read_data,
Delay_data_in => delay_data_in,
Delay_rw_n => delay_rw_n,
Lb_data_out => lb_data_out);

b2v_PIPE_STAGE1 : pipe_stage
GENERIC MAP(ASIZE => 18,BWSIZE => 4,DSIZE => 18)
PORT MAP(Clk => CLK,
Reset => RESET,
Rd_wr_n => RD_WR_N,
Addr_adv_ld_n => ADDR_ADV_LD_N,
Addr => ADDR,
Data_in => DATA_IN,
Data_out => lb_data_out,
Dm => DM,
Rd_wr_n_reg => rd_wr_n_reg,
Addr_adv_ld_n_reg => addr_adv_ld_n_reg,
Addr_reg => addr_reg,
Data_in_reg => data_in_reg,
Data_out_reg => DATA_OUT,
Dm_reg => dm_reg);

END;
 
In my toplevel-file (schematic) the components do have
Generic width on their ports (I am using QuartusII software).

All components symbols have a PARAMATERS BOX in which the value
of the Generics can be defined (Mark Symbol of component --> Symbol
Properties ---> Parameter Name: DSIZE / Setting:18 ...

When I create a VHDL file of the schematic top level file
(Quartus : ---> FILE ---> CREATE ---> VHDL File)
you get the VHDL file shown above.
It seems that Quartus has replaced the Generic input/output widths
of the components. But still there is a GENERIC MAP statement
in the created VHDL file.
And of course the compiler will not be able to handle that if
there is no Generic Declaration in the VHDL top level file.

What to do?

Thank you for your help.
 
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0406242255.42b48559@posting.google.com>...

ENTITY zbt_ctrl_top IS
port
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
Click to expand...
This entity has no generic clause.
You can't do a generic map on an instance
when the base entity has no generic to map.

Something like:

ENTITY zbt_ctrl_top IS
GENERIC (ASIZE : natural;BWSIZE: natural);
port( ...


Also consider using direct instances
to elimainate the component declarations.

-- Mike Treseler
 
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