Generic package

hi,

is it possible to define a package with a generic option

i would like to have this :

package decoder is

generic (N : natural)

type POLY_TAB is array(0 to N) of std_logic_vector(7 downto 0);
....


thanks

 

[KJ]

<patrick.melet@dmradiocom.fr> wrote in message
news:1158049672.511136.278350@m73g2000cwd.googlegroups.com...

hi,

is it possible to define a package with a generic option

i would like to have this :

package decoder is

generic (N : natural)

type POLY_TAB is array(0 to N) of std_logic_vector(7 downto 0);
...

The short answer is 'no you can't put the generic in the package'. But the
following might work for you instead...

package decoder is
type POLY_TAB is array(natural range <&gt of std_logic_vector(7 downto 0);
end package decoder;

Now type 'POLY_TAB' is an unconstrained array. At some point you'll want to
use it and you would declare a signal as...

signal My_Poly_Tab: POLY_TAB(0 to 5);

KJ

 

[Andy]

For now, KJ's approach is a close as you can get. But I believe the
next balloted revision of VHDL is due to have generic packages. Then
the vendors will have to update their tools to support it...

Andy


KJ wrote:

patrick.melet@dmradiocom.fr> wrote in message
news:1158049672.511136.278350@m73g2000cwd.googlegroups.com...
hi,

is it possible to define a package with a generic option

i would like to have this :

package decoder is

generic (N : natural)

type POLY_TAB is array(0 to N) of std_logic_vector(7 downto 0);
...


The short answer is 'no you can't put the generic in the package'. But the
following might work for you instead...

package decoder is
type POLY_TAB is array(natural range <&gt of std_logic_vector(7 downto 0);
end package decoder;

Now type 'POLY_TAB' is an unconstrained array. At some point you'll want to
use it and you would declare a signal as...

signal My_Poly_Tab: POLY_TAB(0 to 5);

KJ

 

thank you KJ

the solution you give works fine....

 

[David Bishop]

patrick.melet@dmradiocom.fr wrote:

hi,

is it possible to define a package with a generic option

i would like to have this :

package decoder is

generic (N : natural)

type POLY_TAB is array(0 to N) of std_logic_vector(7 downto 0);
...

It turns out that this is a feature of VHDL-2006.

Take a look at the code at:
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/files.html