generic gate netlist using Precision RTL

[Vlad Ciubotariu]

Hi all,

I'm using Precision RTL for vhdl synthesis.

Is is possible to generate a technology independent netlist from a vhdl
design? Certain operators such as +, * etc could be left as black boxes.

I need this for setting up a verification toolchain.

thanks,
vlad

 

[Mike Treseler]

Vlad Ciubotariu wrote:

Is is possible to generate a technology independent netlist from a vhdl
design?

That is about what the RTL viewer does.

-- Mike Treseler

 

[HT-Lab]

"Vlad Ciubotariu" <vcciubot@uwaterloo.ca> wrote in message
newsan.2007.04.19.22.50.46.640125@uwaterloo.ca...

Hi all,

I'm using Precision RTL for vhdl synthesis.

Is is possible to generate a technology independent netlist from a vhdl
design? Certain operators such as +, * etc could be left as black boxes.

I checked the reference manual on my version and I don't believe you can.
The only thing you might be able to do is to select the simplest FPGA and
then write you own set of synthesisable primitives thus re-creating a
technology independent netlist.

I need this for setting up a verification toolchain.

Can you explain this?

Hans
www.ht-lab.com

thanks,
vlad

 

[Vlad Ciubotariu]

I need this for setting up a verification toolchain.


Can you explain this?

I'm in the field of formal methods, currently trying a verify a pipelined
microprocessor at the RTL level.

Translating the design into a hierarchical netlist is my prerequisite to
apply symbolic reachability analysis on the design.

vlad

 

[Vlad Ciubotariu]

This tcl script creates 2 edif files:

set_results_dir uw_tmp
setup_design -manufacturer Altera -family {Stratix II} -part EP2S15F484C -speed 5
setup_design -frequency 500
setup_design -design openrisc
setup_design -architecture main
add_input_file <file1>
add_input_file <file2>
........................
compile
auto_write uw_tmp/project_rtl.vhd
auto_write uw_tmp/project_rtl.edf
synthesize
exit

The one project_rtl.edf is the most closely to what I need, but it's not
the same as the way the design is shown in the rtl viewer.

vlad



On Thu, 19 Apr 2007 22:31:09 -0700, Mike Treseler wrote:

Vlad Ciubotariu wrote:

Is is possible to generate a technology independent netlist from a vhdl
design?

That is about what the RTL viewer does.

-- Mike Treseler

 

[HT-Lab]

"Vlad Ciubotariu" <vcciubot@uwaterloo.ca> wrote in message
newsan.2007.04.20.14.34.42.701778@uwaterloo.ca...

I need this for setting up a verification toolchain.


Can you explain this?

I'm in the field of formal methods, currently trying a verify a pipelined
microprocessor at the RTL level.

Translating the design into a hierarchical netlist is my prerequisite to
apply symbolic reachability analysis on the design.

Quite a challenge, not sure if it is any help to you but Precision can write
out a Formal Verification Interface file (FVI) which is used by FormalPro
(equivalence checker). It contains info like used FSM encoding style,
registers removed/inserted etc which might be of some use to you.

Hans
www.ht-lab.com

vlad