generating schematic from extracted views

[Chalam Pattam]

While using some of the tools kits I have noticed schematics missing,
but do have extracted views, In this case we can generate a
synthesised verilog netlist and then import it to cadence and generate
the schematic.

Here are the steps:

1) First of all you need to open up the cell in extracted view
for which you
want a schematic.

2) Click Tools->Verilog-XL, click the Run button, What this does
it creates a
netlist of the extracted view in the "Run Directory" as mentioned in
Setup
Environment.

3) Copy the verilog netlist file located at "Run
Directory"/ihnl/cds0/netlist
to a file name suppose "schematic.v".

4) Now in the main CIW window of cadence click File-> Import ->
Verilog

5) Do create a test library which you can put in the "Target
Library Name" in
Verilog input popup., in "Reference Libraries" I had to include "My
toolkit LibraryName" and
in "Verilog Files to Import" put the file saved as in step 3
(schematic.v).

6) Apply and your schematic should be created in the "Target
Library Name" as
you mentioned.

For making 100% sure the schematic is correct run and LVS with the
created
schematic.