generating clocks

Hi
I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks of 150MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll core since it does not generate the exact clock. If i concatenate two cores, the second core does not produce clock. ( i set one core with input clock as external and other as hardwired). I need help to produce these 3 clocks.

 

[Tim Wescott]

On Sun, 10 Nov 2013 00:54:56 -0800, eyecatcherdear wrote:

Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks
of 150MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll
core since it does not generate the exact clock. If i concatenate two
cores, the second core does not produce clock. ( i set one core with
input clock as external and other as hardwired). I need help to produce
these 3 clocks.

Do they have to be synchronized somehow? Do they have to be generated on-
chip? Do they need to be extra high precision? Can they be extra-low
precision?

A brute-force method, if you have board space and don't want to spend
time messing with the FPGA, is to just use three oscillators.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Richard Damon]

On 11/10/13, 3:54 AM, eyecatcherdear@gmail.com wrote:

Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3
clocks of 150MHz, 112.5MHz and 14.063MHz. I can't produce them with
one pll core since it does not generate the exact clock. If i
concatenate two cores, the second core does not produce clock. ( i
set one core with input clock as external and other as hardwired). I
need help to produce these 3 clocks.

First, realize that you will NEVER get EXACT frequencies, if only
because your input frequency input won't be exact (hopefully fairly
close if it is a crystal, but all sources have errors).

You also don't need exact, but the thing that needs the clock should
have specs for how close it needs to be (and sometimes it is a "not to
exceed" limit for things like processor or memory clocks). Using this
you may well find that one PLL can generate all the frequencies.

If your 150 and 112.5 can be ever so slightly high, then one choice
would be to use an internal frequencey of 450.016 MHz (14.063*32) and
then divide that by 3 and 4 for the two high speed clocks, which puts
them less than 36 ppm high.

 

@Tim Wescott: Yes they have to be generated on core. Actually I need these clocks to implement 3/4 punctured coding with output data rate as 150MHz. 150 and 112.5 are not of very high precision when generated from one core.

@Richard Damon: Yeah I agree to that. But atleast closer. I am going to try your method but you said "internal frequencey of 450.016 MHz (14.063*32) and
then divide that by 3 and 4 for the two high speed clocks, which puts
them less than 36 ppm high." I don't understand the last part. Why is it required to put them less than 36ppm high?

Is there any document you can recommend for clock generation which discusses the PLL clock cores in detail? I get confused with multiple clock generation.

I was wondering if I cascade two cores? The user guide says it allows to generate 6 clocks that means 2 cores.
I tried that using one to generate 150MHz and then generate 112.5 and 14.063 from 150 but the last 2 clocks did not generate.

 

[rickman]

On 11/12/2013 5:28 AM, eyecatcherdear@gmail.com wrote:

@Tim Wescott: Yes they have to be generated on core. Actually I need these clocks to implement 3/4 punctured coding with output data rate as 150MHz. 150 and 112.5 are not of very high precision when generated from one core.

@Richard Damon: Yeah I agree to that. But atleast closer. I am going to try your method but you said "internal frequencey of 450.016 MHz (14.063*32) and
then divide that by 3 and 4 for the two high speed clocks, which puts
them less than 36 ppm high." I don't understand the last part. Why is it required to put them less than 36ppm high?

Is there any document you can recommend for clock generation which discusses the PLL clock cores in detail? I get confused with multiple clock generation.

I was wondering if I cascade two cores? The user guide says it allows to generate 6 clocks that means 2 cores.
I tried that using one to generate 150MHz and then generate 112.5 and 14.063 from 150 but the last 2 clocks did not generate.

A PLL generates clocks by running a voltage controlled oscillator (VCO)
at a rate typically higher than a reference input clock, dividing this
clock rate down and then using a phase comparator to compare to the
input clock. The action of the phase comparator output brings the
frequency of the divided VCO clock to the same rate as the reference and
the output of the PLL to a multiple of the reference clock.

Once you have this output clock you can divide the rate down by any
amount you wish. It would make sense to have a reference clock equal to
one of the input clock rates, but 25 MHz is a nicer rate, not so high as
to be hard to distribute and high enough for most PLLs. Many FPGAs have
a minimum input frequency spec of 25 MHz or so. Or you could use 50 MHz.

Set your PLL to generate 450 MHz. Then you can simply divide this clock
down to generate the three internal clocks of 150, 112.5 and 14.063 MHz
(divide by 3, 4 and 32). You say the FPGA PLL can generate up to 3
clock outputs. If they have programmable dividers for each of the three
outputs you should be able to generate all three frequencies from one
reference input.

The only problem I see is that the 150 MHz requires a divider of 3 from
450 MHz. It is common to use a programmable divider followed by a
divide by 2 to give a symmetrical clock waveform (50/50 duty cycle). So
you might not be able to generate 150 MHz from 450 MHz using the build
in dividers. You can fix this by ramping up the PLL output rate to 900
MHz, using a divider external to the PLL (if it will let you bring the
450 MHz out) or you can just use a second PLL with the same input
reference to generate say, 300 MHz internally and divide by 4.

Is that clear? PLLs have limitations and you need to work with those.

--

Rick

 

[Richard Damon]

On 11/12/13, 5:28 AM, eyecatcherdear@gmail.com wrote:

@Tim Wescott: Yes they have to be generated on core. Actually I need
these clocks to implement 3/4 punctured coding with output data rate
as 150MHz. 150 and 112.5 are not of very high precision when
generated from one core.

@Richard Damon: Yeah I agree to that. But atleast closer. I am going
to try your method but you said "internal frequencey of 450.016 MHz
(14.063*32) and then divide that by 3 and 4 for the two high speed
clocks, which puts them less than 36 ppm high." I don't understand
the last part. Why is it required to put them less than 36ppm high?

My comment on less than 36 ppm high is that the actual number for this
is a bit less than 36 ppm, so it show the error that you WILL get, you
need to see if that is good enough.

Is there any document you can recommend for clock generation which
discusses the PLL clock cores in detail? I get confused with multiple
clock generation.

I was wondering if I cascade two cores? The user guide says it
allows to generate 6 clocks that means 2 cores. I tried that using
one to generate 150MHz and then generate 112.5 and 14.063 from 150
but the last 2 clocks did not generate.

The chip document should have the information needed.

 

Thanks for all that info. I totally understand the PLL phenomenon but the core has a limitation of generating clocks from 0 to 350MHz. I am using Actel Libero IDE evaluation version 9.1. The input clock rate of PROASIC3 is 40MHz.

I can't find any such document where more than one core is used to generate clocks or anyway to produce such clocks in actel.
(The actel PLL core lets you enter your required frequency and then generates the clock with the highest precision unlike xilinx ISE where you have to place dividers and multipliers).

I'll keep looking and trying different approaches with PLL.
Thanks anyway for all your help.