Generating clock delays

[chuk]

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference
-using the wait until statement though this is not supported by Xilinx
for some reason
-using the dll (is this the most efficient manor?)

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

 

[Mario Trams]

chuk wrote:

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference

Yes, synthesis ignores after statements generally.

-using the wait until statement though this is not supported by Xilinx
for some reason

That's basically the same problem as with "after".

-using the dll (is this the most efficient manor?)

That's the way to go - provided that your FPGA implements
such a circuitry. DLLs are there for exactly such purposes.

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

Another alternative is to feed the clock through some normal
circuitry. But you can't describe this in VHDL. Instead, you
need to create a hard-macro that does nothing more than
propagating the signal from input to output. Depending on the
timing information you receive in the data sheets, you can
calculate how often the signal needs to be feed through some
LUTs or other parts.
Although this method is not the very best one, it is working
fine in many cases.

Regards,
Mario

 

[Rene Tschaggelar]

chuk wrote:

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference
-using the wait until statement though this is not supported by Xilinx
for some reason
-using the dll (is this the most efficient manor?)

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

The usual approach for such a problem is to have a PLL.
There are chips, such as the Cypress CY7B9911 clock skew buffer,
or the Cypress CY7B9930 multi frequency PLL clock buffer.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Peter Alfke]

The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager)
is the way to go.
You feed it a continuously-running clock, and you generate outputs that
are delayed by a fraction of the clock period ( defined as integer
multiple of clock period divided by 256). Works very nicely!
Peter Alfke, Xilinx

chuk wrote:

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference
-using the wait until statement though this is not supported by Xilinx
for some reason
-using the dll (is this the most efficient manor?)

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

 

[Andy Peters]

charlesg77@yahoo.com (chuk) wrote in message news:<faa526d6.0401150231.2eae1819@posting.google.com>...

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference

Go re-read the synthesis tool documentation, especially the part about
which VHDL language features are supported and which ones aren't.

"after" isn't. Spend a moment or two thinking about WHY. Hint: Think
Hardware.

-using the wait until statement though this is not supported by Xilinx
for some reason

See above.

-using the dll (is this the most efficient manor?)

That's one way of doing it.

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

Perhaps rather than delaying the clock in such a manner, you need a
higher-frequency master clock that you can use to clock your whole
design. A simple state machine or whatever can be used to create
clock enables at the appropriate time.

-a

 

[Rene Tschaggelar]

Peter,
out of curiosity, how many of these DLLs are in there ?
1, 10, one per pin ?

Rene

Peter Alfke wrote:

The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager)
is the way to go.
You feed it a continuously-running clock, and you generate outputs that
are delayed by a fraction of the clock period ( defined as integer
multiple of clock period divided by 256). Works very nicely!
Peter Alfke, Xilinx

chuk wrote:

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference
-using the wait until statement though this is not supported by Xilinx
for some reason
-using the dll (is this the most efficient manor?)

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks

 

[Peter Alfke]

Between 4 and 12 DCMs in Virtex-II (depending on the chip size).
It's on page 2 of the data sheet. We are not shy in bragging about these
things.
Peter Alfke
=============================
Rene Tschaggelar wrote:

Peter,
out of curiosity, how many of these DLLs are in there ?
1, 10, one per pin ?

Rene

Peter Alfke wrote:
The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager)
is the way to go.
You feed it a continuously-running clock, and you generate outputs that
are delayed by a fraction of the clock period ( defined as integer
multiple of clock period divided by 256). Works very nicely!
Peter Alfke, Xilinx

chuk wrote:

Generating clock delays

I am relatively new to VHDL so pleas excuse me if this is too easy a
question. I need to be able to generate a time shifted version of the
clk signal for control purposes in an Xilinx based project. There are
several options that I have come across:

-Using the after ??n, but this dose not seem to generate any
difference
-using the wait until statement though this is not supported by Xilinx
for some reason
-using the dll (is this the most efficient manor?)

I would like someone to tell me which is the best and most
controllable manor of generating a clock delay. Thanks