Generating a flag signal for first reset only

[tsu]

Hi

I have a DUT that receives series of resets. But, the DUT has to mask
all resets except the first one. Immediately after receiving the first
reset, a flag has to be asserted and it should stay high forever. Any
ideas on how to write synthesizable code for this logic?
The DUT ports are
inputs: clk, reset
output: flag

Regards,
Sujith

 

[Mike314]

On Mar 24, 4:15 pm, tsu <sujithredd...@gmail.com> wrote:

Hi

I have a DUT that receives series of resets. But, the DUT has to mask
all resets except the first one. Immediately after receiving the first
reset, a flag has to be asserted and it should stay high forever. Any
ideas on how to write synthesizable code for this logic?
The DUT ports are
 inputs: clk, reset
 output: flag

Regards,
Sujith

It is not achievable unless you have second reset signal or have some
other indication (like an analog POR).

 

[News123]

This is not possible for any generic silicon.

It would be possile for an FPGA implementation.
FPGAs have defined reset values of registers after being programmed.

Some technologies have RAM cells with defined values after power up.
Perhaps you have special hold cells who hold signals stronger than an
external pull up.

If not, then you would need an external 'power up reset' signal.


The verilog equivalent for FPGAs, that initialize regs with 0 should be
the cod below. (I did not test the code)

reg got_first_reset; // 1'b1 if first reset has occurred
// (been released)

// depending on the synthesis tools the two initial statements
// had to me undefed / commented for synthesis.
initial got_first_reset = 1'b0;
initial first_cycle_after_reset = 1'b0;

reg first_cycle_after_a_reset; // indicates first clock cycle after
// reset has been released
reg data_to_reset_once;

always @(posedge clk or negedge async_reset) begin
if(!async_reset) begin
if(!got_first_reset) data_to_reset_once <= 1'b0;
first_cycle_after_reset <= 1'b1;
end
else begin
if(first_cycle_after_a_reset) begin
got_first_reset <= 1'b1;
first_cycle_after_a_reset <= 1'b0; // only needed
// to be true to reg name

end
// FUNCTIONL STUFF
end
end


bye


N

Mike314 wrote:

On Mar 24, 4:15 pm, tsu <sujithredd...@gmail.com> wrote:
Hi

I have a DUT that receives series of resets. But, the DUT has to mask
all resets except the first one. Immediately after receiving the first
reset, a flag has to be asserted and it should stay high forever. Any
ideas on how to write synthesizable code for this logic?
The DUT ports are
inputs: clk, reset
output: flag

Regards,
Sujith

It is not achievable unless you have second reset signal or have some
other indication (like an analog POR).

 

[tsu]

On Mar 25, 11:22 am, News123 <news...@free.fr> wrote:

This is not possible for any generic silicon.

It would be possile for an FPGA implementation.
FPGAs have defined reset values of registers after being programmed.

Some technologies have RAM cells with defined values after power up.
Perhaps you have special hold cells who hold signals stronger than an
external pull up.

If not, then you would need an external  'power up reset' signal.

The verilog equivalent for FPGAs, that initialize regs with 0 should be
the cod below. (I did not test the code)

reg got_first_reset; // 1'b1 if first reset has occurred
                     // (been released)

// depending on the synthesis tools the two initial statements
// had to me undefed / commented for synthesis.
initial got_first_reset = 1'b0;
initial first_cycle_after_reset = 1'b0;

reg first_cycle_after_a_reset; // indicates first clock cycle after
                               // reset has been released
reg data_to_reset_once;

always @(posedge clk or negedge async_reset) begin
     if(!async_reset) begin
          if(!got_first_reset) data_to_reset_once <= 1'b0;
          first_cycle_after_reset <= 1'b1;
     end
     else begin
         if(first_cycle_after_a_reset) begin
             got_first_reset <= 1'b1;
             first_cycle_after_a_reset <= 1'b0; // only needed
                                      // to be true to reg name

         end
         // FUNCTIONL STUFF
     end
end

bye

N



Mike314 wrote:
On Mar 24, 4:15 pm, tsu <sujithredd...@gmail.com> wrote:
Hi

I have a DUT that receives series of resets. But, the DUT has to mask
all resets except the first one. Immediately after receiving the first
reset, a flag has to be asserted and it should stay high forever. Any
ideas on how to write synthesizable code for this logic?
The DUT ports are
 inputs: clk, reset
 output: flag

Regards,
Sujith

It is not achievable unless you have second reset signal or have some
other indication (like an analog POR).- Hide quoted text -

- Show quoted text -

In my platform "initial block" is synthesizable. I used initial to
generate the flag. Thanks a lot for the provided inputs.

Regards,
TSU

 

[hairyotter]

Out of curiosity, what platform is that ?

Thanks, Marco.