generated (divided) clocks with Encounter RTL compiler ?

[m]

hi,
does cadence encounter rtl compiler support generated clocks. I have a
clock divider which I constrain with set_clock_info_change in
Buildgates but I can't find a corresponding command in RC
documentation.

 

[m]

On Tue, 31 May 2005 20:52:47 GMT, mk<kal*delete@dspia.*comdelete>
wrote:

hi,
does cadence encounter rtl compiler support generated clocks. I have a
clock divider which I constrain with set_clock_info_change in
Buildgates but I can't find a corresponding command in RC
documentation.

It turns out one can write an SDC script with the synopsys design
constraint command create_generated_clock in it and read it with
read_sdc. This way timing and clock -generated reports seem to suggest
that the divided clock constraint works. But alas the same design
gives a much worse result with RTL compiler than with latest
Buildgates synthesizer with -stop_before placement option. Also so far
I couldn't figure out how to introduce a LEF to the RTL compiler. I
was hopeful about the RTL compiler but so far I am disappointed.