B
bir
Guest
In VHDL we use GENERATE for conditional creation of components. What do
we use in verilog for this??
Thanks
we use in verilog for this??
Thanks
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A
Ajeetha
Guest
Verilog 2001 added similar generate into the language. Do a google for
"Verilog generate".
HTH
Ajeetha, CVC
www.noveldv.com
bir wrote:
"Verilog generate".
HTH
Ajeetha, CVC
www.noveldv.com
bir wrote:
In VHDL we use GENERATE for conditional creation of components. What do
we use in verilog for this??
Thanks
R
Ralf Hildebrandt
Guest
bir schrieb:
VHDL generate by the use of Verilog parameters. But VHDL generate is
much more capable. In Verilog by the use of parameters you let the
synthesis tool do the job of optimizing unused things away.
Ralf
For old Verilog it is possible to do some things you can achieve withIn VHDL we use GENERATE for conditional creation of components. What do
we use in verilog for this??
VHDL generate by the use of Verilog parameters. But VHDL generate is
much more capable. In Verilog by the use of parameters you let the
synthesis tool do the job of optimizing unused things away.
Ralf