Generate statements

[GaLaKtIkUs™]

I have written a complex verilog code which describes a generic module.
These parameters are used in generate blocks.
I use parameters to configure the top level module, the parameters are
propagated to the tree of submodules.
I would like to distribute the source code for my module but just for a
particular case of input parameters: Is there some program which can
execute all the generate loops/conditions and give me as output a
verilog code without all the generate blocks?

Cheers

 

[Muks]

If you are using VCS then you can generate tokens.v in verilog-95.
You can use compile time switch -Xman=2 with VCS and it will generate
tokens.v in verilog format without having generate.

Thanks
Mukesh

GaLaKtIkUs™ wrote:

I have written a complex verilog code which describes a generic module.
These parameters are used in generate blocks.
I use parameters to configure the top level module, the parameters are
propagated to the tree of submodules.
I would like to distribute the source code for my module but just for a
particular case of input parameters: Is there some program which can
execute all the generate loops/conditions and give me as output a
verilog code without all the generate blocks?

Cheers

 

[GaLaKtIkUs™]

Unfortunately I don't have VCS
Any other proposition?

Muks wrote:

If you are using VCS then you can generate tokens.v in verilog-95.
You can use compile time switch -Xman=2 with VCS and it will generate
tokens.v in verilog format without having generate.

Thanks
Mukesh

GaLaKtIkUs™ wrote:
I have written a complex verilog code which describes a generic module.
These parameters are used in generate blocks.
I use parameters to configure the top level module, the parameters are
propagated to the tree of submodules.
I would like to distribute the source code for my module but just for a
particular case of input parameters: Is there some program which can
execute all the generate loops/conditions and give me as output a
verilog code without all the generate blocks?

Cheers

 

You can run it through a language translater Verilog->VHDL->Verilog

Each translation removes (unrolls) any language-specific constructs,
and expands your defines.

The resulting code will be almost unreadable, you get to decide if this
is important.

GH