Generate statements for I/O list

J

John_H

Guest
(I meant to post this originally here, not on comp.arch.fpga)

Greetings,

I want to parameterize a module in a way that makes some inputs used or
not used. If I have the input defined but don't use it in the module
instantiation, I end up with a synthesis warning about tying an unused
input to 0. If I use a generate, I'll be trying to add a generate item
of the form "input clk," where the comma looks like it won't be a legal
generate item.

Anyone have a clean way to remove the input from the module definition
list without a `define?

I can imagine specifying a Verilog-1995 style I/O list where only the
names are listed initially then outside the module port definition use
an if/else to define my value as input or output; if I don't use the
output, I get no warning and if I hook something up to the signal I want
unused I should have a synthesis warning for too many drivers. But I'd
like to keep my Verilog-2001 style of I/O definitions embedded in the
portdefs.

- John_H
 
On Wed, 02 Aug 2006 01:50:12 GMT, John_H
<johnhandwork@mail.com> wrote:

I want to parameterize a module in a way that makes some inputs used or
not used. If I have the input defined but don't use it in the module
instantiation, I end up with a synthesis warning about tying an unused
input to 0. If I use a generate, I'll be trying to add a generate item
of the form "input clk," where the comma looks like it won't be a legal
generate item.
Click to expand...
No, you definitely can't use 'generate' to do this.

You could get rid of the synthesis warnings by explicitly tying-off
any unused inputs to constant values, I suppose. VHDL lets you
do that by putting default constant values on input ports, but
in Verilog you must do it explicitly in the module instantiation.

In SystemVerilog you could bundle most of your I/O as an "interface",
pass an instance of that interface through a single port, and then
use generate in both the interface and the module to configure
the required set of connections in any given instance. This sounds
like a great idea, but in practice it's the door to a whole new world
of pain; its usefulness would depend strongly on the details of
what you're trying to do.

It would be interesting to see a bit more detail of what you are
aiming for. Is the set of ports really something that you could
expect to describe with a few parameters? If so, can't you get
the same effect with suitably configurable array ports?
Sometimes it's better just to settle for a collection of
different modules, and use generate...case to choose which
one you instantiate.

It would be good to discuss this in a bit more detail, so that
others in the group can offer alternative solutions. We have
had similar queries from customers in the past, without
reaching any clear conclusions.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi,
Just to add on. In DC, unused ports can be removed through
remove_unused_ports.

Best regards,
ABC

Jonathan Bromley wrote:
On Wed, 02 Aug 2006 01:50:12 GMT, John_H
johnhandwork@mail.com> wrote:

I want to parameterize a module in a way that makes some inputs used or
not used. If I have the input defined but don't use it in the module
instantiation, I end up with a synthesis warning about tying an unused
input to 0. If I use a generate, I'll be trying to add a generate item
of the form "input clk," where the comma looks like it won't be a legal
generate item.

No, you definitely can't use 'generate' to do this.

You could get rid of the synthesis warnings by explicitly tying-off
any unused inputs to constant values, I suppose. VHDL lets you
do that by putting default constant values on input ports, but
in Verilog you must do it explicitly in the module instantiation.

In SystemVerilog you could bundle most of your I/O as an "interface",
pass an instance of that interface through a single port, and then
use generate in both the interface and the module to configure
the required set of connections in any given instance. This sounds
like a great idea, but in practice it's the door to a whole new world
of pain; its usefulness would depend strongly on the details of
what you're trying to do.

It would be interesting to see a bit more detail of what you are
aiming for. Is the set of ports really something that you could
expect to describe with a few parameters? If so, can't you get
the same effect with suitably configurable array ports?
Sometimes it's better just to settle for a collection of
different modules, and use generate...case to choose which
one you instantiate.

It would be good to discuss this in a bit more detail, so that
others in the group can offer alternative solutions. We have
had similar queries from customers in the past, without
reaching any clear conclusions.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:7fq0d2tmu4hebsml8svd7jir9hhv5d2n01@4ax.com...
<snip>
You could get rid of the synthesis warnings by explicitly tying-off
any unused inputs to constant values, I suppose. VHDL lets you
do that by putting default constant values on input ports, but
in Verilog you must do it explicitly in the module instantiation.
snip
Click to expand...

I'd love to exclude the port entirely if it's unused rather than
instantiating with a 1'b0 to avoid the synthesis warning about the unused
input being tied to 0.

<snip>
It would be good to discuss this in a bit more detail, so that
others in the group can offer alternative solutions. We have
had similar queries from customers in the past, without
reaching any clear conclusions.
snip
Click to expand...

I'd like to have a parameter that makes the result pipelined (needing a
clock) or combinatorial (where the clock is meaningless). If the design is
pipelined and a reset is desired, the reset should be included in the
portdefs, otherwise left unconnected.

It looks like SynplifyPro doesn't accept "input clk;" as a generate item in
the module body so my fallback of using the old-style portdef didn't work.

There are no synthesis warnings when I define my clock and reset as inout
and either don't generate an output or don't use the input for the
appropriate modes. I don't get warnings if the parameter says the port
should be there and it's unconnected, however. If there's no connection to
the input of the inout and no assignment for the output of the inout, I end
up with warning-free compile in SynplifyPro which leaves me with potentially
unconnected ports I wanted connected.

Maybe I can't make this an "all things for all people" paramaterized module
where clk and rst are optional port values that give a warning if you don't
use needed ports or use unneeded ports.
 
Welcome to the club. At the end of the, day there is no benefit in
pushing current HDL languages and tools beyond its limit.

John_H wrote:
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:7fq0d2tmu4hebsml8svd7jir9hhv5d2n01@4ax.com...
snip
You could get rid of the synthesis warnings by explicitly tying-off
any unused inputs to constant values, I suppose. VHDL lets you
do that by putting default constant values on input ports, but
in Verilog you must do it explicitly in the module instantiation.
snip

I'd love to exclude the port entirely if it's unused rather than
instantiating with a 1'b0 to avoid the synthesis warning about the unused
input being tied to 0.

snip
It would be good to discuss this in a bit more detail, so that
others in the group can offer alternative solutions. We have
had similar queries from customers in the past, without
reaching any clear conclusions.
snip

I'd like to have a parameter that makes the result pipelined (needing a
clock) or combinatorial (where the clock is meaningless). If the design is
pipelined and a reset is desired, the reset should be included in the
portdefs, otherwise left unconnected.

It looks like SynplifyPro doesn't accept "input clk;" as a generate item in
the module body so my fallback of using the old-style portdef didn't work.

There are no synthesis warnings when I define my clock and reset as inout
and either don't generate an output or don't use the input for the
appropriate modes. I don't get warnings if the parameter says the port
should be there and it's unconnected, however. If there's no connection to
the input of the inout and no assignment for the output of the inout, I end
up with warning-free compile in SynplifyPro which leaves me with potentially
unconnected ports I wanted connected.

Maybe I can't make this an "all things for all people" paramaterized module
where clk and rst are optional port values that give a warning if you don't
use needed ports or use unneeded ports.
Click to expand...
 
Jim_B wrote:
Welcome to the club. At the end of the, day there is no benefit in
pushing current HDL languages and tools beyond its limit.
Click to expand...
I didn't think this an unreasonable thing to do, accommodated within the
limits available to the language. It appears I was wrong.
 
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