Generate schematic from netlist?

[newsleecher@spam.com]

Is there a tool that will take a structural verilog netlist as input
and generate a schematic or block diagram in some image format
corresponding to the netlist, with labeled blocks, ports, and nets?

I designed a CPU for a class project last semester and have a bunch
of hand drawn schematics I would like to convert to electronic form.
Scanning won't work because the drawings are a mess and are not
entirely complete either.

I thought about using a tool like Visio to create the block
diagrams, but I have a feeling I may need to modify this design
later, and I would not want to have to keep manually editing the
visio diagrams every time I make a change to the verilog code.

So in short, is there a tool that will do what I describe in the
first paragraph?


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Is there a tool that will take a structural verilog netlist as input
and generate a schematic or block diagram in some image format
corresponding to the netlist, with labeled blocks, ports, and nets?

I designed a CPU for a class project last semester and have a bunch
of hand drawn schematics I would like to convert to electronic form.
Scanning won't work because the drawings are a mess and are not
entirely complete either.

I thought about using a tool like Visio to create the block
diagrams, but I have a feeling I may need to modify this design
later, and I would not want to have to keep manually editing the
visio diagrams every time I make a change to the verilog code.

This is a very interesting question. Do you consider your original
source to be the Verilog or the schematic diagrams? As I understand
it, you want them to contain the same information.

This sounds like a bad idea, if only because a design with conflicting
information is usually more trouble than a design with a mistake.

I understand that you're in an artificial situation (preparing
documents for a class), but may you should ask your teachers to
justifiy creating source documents in both forms (if that's what
they've asked you to do).

When speaking to people who've no experience of an HDL (written as
text, like Verilog or VHDL), I find a lot of unease about designing
other than with schematic diagrams. This is understandable, because
it's what we all had to do in the past. It takes time to be as
relaxed with a text design as with a schematic. Perhaps you're in the
same situation.

Writing in an HDL is much more like writing software than the old
methods of hardware design. For an HDL, the same skills are important
(like how best to divide a design into modules, how best to design the
interfaces between them, how to achieve loose coupling of modules).
Traditionally, the standard of hardware documentation has also been
poorer (e.g. unnamed signals on a diagram - equivalent to using
variable names like X and XX in software), perhaps because less
attention has been paid to the quality of schematic designs. (It's
also more difficult to have extensive comments in a diagram).

Given this similarity, some people suggest that it's best to have a
block diagram schematic only at the top level and text HDL (with no
diagrams) below that. Perhaps you can solve your maintenance problem
by making that top-level diagram sufficiently "top-level" that it
rarely needs to be updated.

I find it easier to maintain a good text file than a good block
diagram, but others may find the reverse, so you should choose the
format with which you feel more comfortable. You may need to convert
manually from a schematic to to HDL (so you can synthesise your
design), but I don't see any practical use for converting HDL to a
schematic, except to document the design for people who can't read the
HDL. I'm not sure that the conversion for those people needs to be
all that accurate anyway. It doesn't sound like they're going to be
deeply involved in maintenance. You mention updating the schematics
from the Verilog, so it's clear that you already feel more at ease
changing the HDL design than in starting from the schematics. Those
schematics are obviously going to be neglected, so maybe it's time to
abandon them formally.

 

[Mike Treseler]

newsleecher@spam.com wrote:

Is there a tool that will take a structural verilog netlist as input
and generate a schematic or block diagram in some image format
corresponding to the netlist, with labeled blocks, ports, and nets?

The tools are going the other way.
The quartus RTL viewer will take an HDL description and draw
a very nice schematic or block diagram for you.
See my posting of 5-12-06

I designed a CPU for a class project last semester and have a bunch
of hand drawn schematics I would like to convert to electronic form.
Scanning won't work because the drawings are a mess and are not
entirely complete either.

Convert the schematic to verilog or vhdl RTL.
This is the most useful electronic form that
there is at the moment.
Put the code up on the RTL viewer to see if you got it right.
Maybe even run a sim.

I thought about using a tool like Visio to create the block
diagrams, but I have a feeling I may need to modify this design
later, and I would not want to have to keep manually editing the
visio diagrams every time I make a change to the verilog code.

Go with your feelings.
Write some code and let the
computer do the tedious stuff.

-- Mike Treseler

 

Is there a tool that will take a structural verilog netlist as input
and generate a schematic or block diagram in some image format
corresponding to the netlist, with labeled blocks, ports, and nets?

Novas' Debussy/Verdi will create a schematic from verilog structural or
rtl code; there are options to save as pdf/jpg etc. [Debussy/Verdi is
much more than a schematic drawer, it just happens to do so as part of
the debug environment it provides].

If you view your verilog source as the master then the generating a
schematic from it as documentation sounds reasonable.

 

Novas' Debussy/Verdi will create a schematic from verilog...
If you view your verilog source as the master then the generating a
schematic from it as documentation sounds reasonable.

This sounds like a "silver bullet". I believe in it like I believe in
the Tooth Fairy.

Development tools convert clear (if you're lucky and/or conscientious)
source into increasingly obscure forms until you have something you
can load to the hardware. You can dream of a tool that will do the
reverse, creating good documents automatically (so you don't have to
write them), but it won't happen.

From time to time, you'll hear of "self-documenting code" and other
such promises of an easy life. You'll even hear how programming tools
will be so good we won't have to write code any more. Well, "see that
ye be not troubled: for all these things must come to pass, but the
end is not yet".

 

[Ajeetha]

Hi,
Modern HDL simulators all can do this for you fairly easily. I've for
sure tried this with VCS and it works (with their new DVE). Structural
is easy, RTL is tougher. But Debussy/Verdi can do that as well.
Sometime back I remember Simvision from Cadence promising similar
capabilities, spend some time @ www.cadence.com - you may get some
insight.

Good Luck
Ajeetha, CVC
www.noveldv.com