K
Kenneth Brun Nielsen
Guest
I want to monitor a (vector) signal and generate a pulse of a
specified length (in time) whenever (any of the bits in) the signal
changes value.
Does VHDL feature a simple way to do that?
A primitive solution would be to XOR each signal bit with a delayed
replica of itself, but I assume that VHDL has better ways of
implementing this?
It does only have to work in simulations.
Best regards,
Kenneth
specified length (in time) whenever (any of the bits in) the signal
changes value.
Does VHDL feature a simple way to do that?
A primitive solution would be to XOR each signal bit with a delayed
replica of itself, but I assume that VHDL has better ways of
implementing this?
It does only have to work in simulations.
Best regards,
Kenneth