Generate instance and net name labels from schematic

[sesi]

Hello all,

Is there any procedure in skill to generate attached labels of
instance names on instances and net names on the nets from the
schematic.
Given that the layout is LVS clean using calibre or assura so that we
get the connectivith information. And here how to get the net
information and instance names from the schematic rather than the
orginal
instance names(cv~>instances~>name) from the layout. Is it possible
through skill or else through Calibre or Assura itself.

 

[Andrew Beckett]

sesi wrote, on 01/13/10 06:09:

Hello all,

Is there any procedure in skill to generate attached labels of
instance names on instances and net names on the nets from the
schematic.
Given that the layout is LVS clean using calibre or assura so that we
get the connectivith information. And here how to get the net
information and instance names from the schematic rather than the
orginal
instance names(cv~>instances~>name) from the layout. Is it possible
through skill or else through Calibre or Assura itself.

Are you talking about updating the layout database to have names on it based on
schematic names?

Are you using Virtuoso Layout Suite XL?

Could you generate an extracted view and then use that to find the corresponding
layout view device?

As you can see, a lot of questions - it's not that clear what you're actually
asking...

Andrew.

 

[sesi]

Hi Andrew,

I want to generate instance names on instances and net names on the
nets in the layout so that it is easy for identiying a device by
seeing the label on the instance and the text label net name on the
net.
So that this could be easy for somebody who is new and reviewing the
layout.
Now here the problem is the the layout instance names and the
schematic instance names need not be same always. ex A device say pmos
w -5microns , l 5-microns in the schematic is lvs matched in the
layout pmos w -5microns , l 5-microns
but the instance name of this pmos need not be same in the layout and
schematic.
To get exact instance names both in the layout and schematic during
floorplaning I am using the option Tools ->Design Synthesis ->Layout
XL option in the schematic window and the option Design->Gen from
source in the corresponding layout XL window. But when ever I copy a
device its instance name is changed as compared to the schematic , and
finally when I complete my layout rarely I found a device in my layout
having same instance name as in the schematic.
Now here are the issues -
After completing LVS cleaned layout how to get the exact instance
names in the layout as in the schematic ,same thing for net names.

I am using Virtuso - XL only for generating the devices , later I move
to Virtuso layout.

 

[Andrew Beckett]

sesi wrote, on 01/15/10 04:35:

Hi Andrew,

I want to generate instance names on instances and net names on the
nets in the layout so that it is easy for identiying a device by
seeing the label on the instance and the text label net name on the
net.
So that this could be easy for somebody who is new and reviewing the
layout.
Now here the problem is the the layout instance names and the
schematic instance names need not be same always. ex A device say pmos
w -5microns , l 5-microns in the schematic is lvs matched in the
layout pmos w -5microns , l 5-microns
but the instance name of this pmos need not be same in the layout and
schematic.
To get exact instance names both in the layout and schematic during
floorplaning I am using the option Tools ->Design Synthesis ->Layout
XL option in the schematic window and the option Design->Gen from
source in the corresponding layout XL window. But when ever I copy a
device its instance name is changed as compared to the schematic , and
finally when I complete my layout rarely I found a device in my layout
having same instance name as in the schematic.
Now here are the issues -
After completing LVS cleaned layout how to get the exact instance
names in the layout as in the schematic ,same thing for net names.

I am using Virtuso - XL only for generating the devices , later I move
to Virtuso layout.

If you're not using Virtuoso XL throughout the flow (which is a wise idea, since
it would then allow you to cross-probe between schematic and layout, making it
much easier for a reviewer), then you'd have to try to get the information about
which device is which from the LVS tool. That's not going to be trivial, because
quite possibly the LVS tool is using the flattened polygons in each device to
identify what kind of transistor it is, and then you've got to try to match this
up to the pcell instance in the layout.

You may be able to query the LVS tool (Assura or Calibre - it will be different
for each) and find out the coordinates where each transistor is, and then look
for instances at that coordinate in the original layout. That _may_ work, but
you might have (say) overlapping devices (particularly when you've got pcells
with large wells, say).

So it doesn't sound that easy to me... compared with getting the data consistent
in the first place, rather than just using XL to do an initial device creation
and no more.

IC614, the binder in VLS XL has now got some nice incremental binding
capabilties, such that devices get matched in the layout against the schematic
as they become unambiguous - so that means it is much better able to work if you
copy parts of the layout - as you hook them up, it figures out which device is
which, and there is much less need to use the Define Device Correspondence form.

Regards,

Andrew.

 

[sesi]

Hi Andrew,

Thanks Andrew for the information ,
Yes , I think it is a complicate process but still do you think is it
possible by quering either assura or calibre.
And regarding XL , I am stopping using that further because , it
displays the DRC information and the blinking markers when a wrong
placement is done and the connectivity lines all these information
creates
disturbance , I feel after the placement virtuso layout , is better
than XL.