generate for loop

B

bil050

Guest
Hi,
I sit possible to write something like this:
Code: 
    genvar i,j;
generate for (i = N;i > 0; i = i - 1)
                 for( j = 0 ; j< i;j = j + 1) begin:dec
                        ......
                 end
endgenerate

[\code]

Thanks,
 
On Jul 20, 6:28 am, bil050 <irinali...@gmail.com> wrote:
Hi,
I sit possible to write something like this:
Click to expand...
You just did!

Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.
 
On Jul 20, 2:00 pm, John_H <newsgr...@johnhandwork.com> wrote:
On Jul 20, 6:28 am, bil050 <irinali...@gmail.com> wrote:

Hi,
I sit possible to write something like this:

You just did!

Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.
Click to expand...
Thank you for your reply!
This will generate two nested genrates?...
 
On Jul 20, 2:23 pm, bil050 <irinali...@gmail.com> wrote:
On Jul 20, 2:00 pm, John_H <newsgr...@johnhandwork.com> wrote:

On Jul 20, 6:28 am, bil050 <irinali...@gmail.com> wrote:

Hi,
I sit possible to write something like this:

You just did!

Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.

Thank you for your reply!
This will generate two nested genrates?...
Click to expand...
May be you can show the example for it?
 
On Tue, 20 Jul 2010 04:00:22 -0700 (PDT), John_H wrote:

Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.
Click to expand...
??? I don't really understand that. I am clear that
the OP's code would indeed generate a "triangular array"
with N instances of the inner loop's body from the first i,
N-1 instances for the second and so on. The only mistake
was that the outer loop also needs a begin...end even though
it contains only the one single "for".

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.
Click to expand...
I don't think you're allowed to nest generate...endgenerate, and
it is definitely not necessary. Since Verilog-2005 you don't
even need the generate/endgenerate keywords, although I usually
put them in to make my intent clear.

Here's a complete example that actually runs, and displays
enough for you to see what's going on. I've coded it so
that it will work in a Verilog-2001 simulator.

module gen;
parameter N = 3;
genvar i,j;
generate
for (i=N; i>0; i=i-1) begin: outer
for (j=0; j<i; j=j+1) begin: inner
initial $display("%m: i=%0d, j=%0d", i, j);
end
end
endgenerate
endmodule

It's also educational to remove the label from one or other
of the loops, and see what happens. That won't work unless
your simulator supports Verilog-2005 or later, and you'll
see why it's a bad idea anyway. Note carefully the output
from %m in the $displays.
--
Jonathan Bromley
 
On Jul 20, 11:35 am, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
On Tue, 20 Jul 2010 04:00:22 -0700 (PDT), John_H wrote:
Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.

??? I don't really understand that.  I am clear that
the OP's code would indeed generate a "triangular array"
with N instances of the inner loop's body from the first i,
N-1 instances for the second and so on.  The only mistake
was that the outer loop also needs a begin...end even though
it contains only the one single "for".

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.

I don't think you're allowed to nest generate...endgenerate, and
it is definitely not necessary.  Since Verilog-2005 you don't
even need the generate/endgenerate keywords, although I usually
put them in to make my intent clear.

Here's a complete example that actually runs, and displays
enough for you to see what's going on.  I've coded it so
that it will work in a Verilog-2001 simulator.

module gen;
  parameter N = 3;
  genvar i,j;
  generate
    for (i=N; i>0; i=i-1) begin: outer
      for (j=0; j<i; j=j+1) begin: inner
        initial $display("%m: i=%0d, j=%0d", i, j);
      end
    end
  endgenerate
endmodule

It's also educational to remove the label from one or other
of the loops, and see what happens.  That won't work unless
your simulator supports Verilog-2005 or later, and you'll
see why it's a bad idea anyway.  Note carefully the output
from %m in the $displays.
--
Jonathan Bromley
Click to expand...
I haven't generated a generate in quite some time but since a
"generate for" is used to replicate the content in its inner loop and
a generate can be inside or outside an always block (can't it?)
wouldn't the result of a single generate block be a repetition of the
internal for statement?

I believe most of my generates came from Verilog-2001.

The untested code I would expect to work would be as follows:

genvar i,j;
generate for (i = N;i > 0; i = i - 1)
generate for( j = 0 ; j< i;j = j + 1)
begin:dec
......
end
endgenerate
endgenerate

I'm happy to be wrong about this.
 
On Jul 21, 2:00 pm, John_H <newsgr...@johnhandwork.com> wrote:
On Jul 20, 11:35 am, Jonathan Bromley <s...@oxfordbromley.plus.com
wrote:





On Tue, 20 Jul 2010 04:00:22 -0700 (PDT), John_H wrote:
Actually what you're showing would generate N for loops, not N(N+1)/2
statements from your inner loop.

??? I don't really understand that.  I am clear that
the OP's code would indeed generate a "triangular array"
with N instances of the inner loop's body from the first i,
N-1 instances for the second and so on.  The only mistake
was that the outer loop also needs a begin...end even though
it contains only the one single "for".

If you want those N(N+1)/2 statements, nest: use two generate for and
two endgenerate statements and you should get what you want.

I don't think you're allowed to nest generate...endgenerate, and
it is definitely not necessary.  Since Verilog-2005 you don't
even need the generate/endgenerate keywords, although I usually
put them in to make my intent clear.

Here's a complete example that actually runs, and displays
enough for you to see what's going on.  I've coded it so
that it will work in a Verilog-2001 simulator.

module gen;
  parameter N = 3;
  genvar i,j;
  generate
    for (i=N; i>0; i=i-1) begin: outer
      for (j=0; j<i; j=j+1) begin: inner
        initial $display("%m: i=%0d, j=%0d", i, j);
      end
    end
  endgenerate
endmodule

It's also educational to remove the label from one or other
of the loops, and see what happens.  That won't work unless
your simulator supports Verilog-2005 or later, and you'll
see why it's a bad idea anyway.  Note carefully the output
from %m in the $displays.
--
Jonathan Bromley

I haven't generated a generate in quite some time but since a
"generate for" is used to replicate the content in its inner loop and
a generate can be inside or outside an always block (can't it?)
wouldn't the result of a single generate block be a repetition of the
internal for statement?

I believe most of my generates came from Verilog-2001.

The untested code I would expect to work would be as follows:

genvar i,j;
generate for (i = N;i > 0; i = i - 1)
  generate for( j = 0 ; j< i;j = j + 1)
    begin:dec
      ......
    end
  endgenerate
endgenerate

I'm happy to be wrong about this.- Hide quoted text -

- Show quoted text -
Click to expand...
Nested generate are not allowed
the solution I used :
genvar i,j;
generate
for( i = `inputNUM - 1; i > 0; i = i - 1)
begin: chip_loop_out
for ( j = 0; j < i; j = j + 1)
begin: chip_loop_in
...
end
end
endgenerate
 
I haven't generated a generate in quite some time but since a
"generate for" is used to replicate the content in its inner loop and
a generate can be inside or outside an always block (can't it?)
Click to expand...
No, it certainly can't. It can be used only at the top level of a
module.

wouldn't the result of a single generate block be a repetition of the
internal for statement?
Click to expand...
Yes, but that "for" is NOT a procedural for-loop; it's a generate loop
that describes static replication of its contents. The "for" syntax
(and, come to that, "if" and "case") were borrowed for use inside
generates, because there can be no confusion; for/if/case are
procedural constructs only when used inside an always or initial
block.

I believe most of my generates came from Verilog-2001.
Click to expand...
Fair enough, but that doesn't alter the basics. V-2005 made some
things a bit more flexible - you can omit generate/endgenerate
keywords, and begin...end block labels in generates can be omitted and
will be created automatically by the compiler. It also tightened up
the rules about scopes and the behaviour of genvar, but that was
mainly to plug some obscure ambiguities and doesn't affect the
standard uses.

The untested code I would expect to work would be as follows:

genvar i,j;
generate for (i = N;i > 0; i = i - 1)
  generate for( j = 0 ; j< i;j = j + 1)
    begin:dec
      ......
    end
  endgenerate
endgenerate

I'm happy to be wrong about this.
Click to expand...
Remove the inner generate and endgenerate, and provide a labelled
begin...end on the outer for-loop, and you're OK.
--
Jonathan Bromley
 
On Jul 21, 1:36 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
I haven't generated a generate in quite some time but since a
"generate for" is used to replicate the content in its inner loop and
a generate can be inside or outside an always block (can't it?)

No, it certainly can't.  It can be used only at the top level of a
module.

wouldn't the result of a single generate block be a repetition of the
internal for statement?

Yes, but that "for" is NOT a procedural for-loop; it's a generate loop
that describes static replication of its contents.  The "for" syntax
(and, come to that, "if" and "case") were borrowed for use inside
generates, because there can be no confusion; for/if/case are
procedural constructs only when used inside an always or initial
block.

I believe most of my generates came from Verilog-2001.

Fair enough, but that doesn't alter the basics.  V-2005 made some
things a bit more flexible - you can omit generate/endgenerate
keywords, and begin...end block labels in generates can be omitted and
will be created automatically by the compiler.  It also tightened up
the rules about scopes and the behaviour of genvar, but that was
mainly to plug some obscure ambiguities and doesn't affect the
standard uses.

The untested code I would expect to work would be as follows:

genvar i,j;
generate for (i = N;i > 0; i = i - 1)
  generate for( j = 0 ; j< i;j = j + 1)
    begin:dec
      ......
    end
  endgenerate
endgenerate

I'm happy to be wrong about this.

Remove the inner generate and endgenerate, and provide a labelled
begin...end on the outer for-loop, and you're OK.
--
Jonathan Bromley
Click to expand...
I appreciate the clarification (since my use is obviously rusty) and
happy that bil050 got his generate working.
 
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