generate block in systemverilog

[ramnarayan]

Hi,
can anyone tell me about generate block in systemverilog , when
we should use it,In
systemverilog lrm itself they have not mentioned clearly.

Thanks in advance

 

[Ajeetha]

Hi Ram,
Generate is part of V2K standard and SV builds on top of it, so
take a look at V2K LRM. Also there are some good papers from Stuart,
Cliff et al on this, do a google search.

Regards
Ajeetha, CVC
www.noveldv.com

ramnarayan wrote:

Hi,
can anyone tell me about generate block in systemverilog , when
we should use it,In
systemverilog lrm itself they have not mentioned clearly.

Thanks in advance

 

ramnarayan wrote:

can anyone tell me about generate block in systemverilog , when
we should use it,In
systemverilog lrm itself they have not mentioned clearly.

That is because they are not a SystemVerilog extension. They are part
of Verilog-2001. You should look at a Verilog LRM.