Generate a output pulse from 3 difference triggers

[Cuthbert]

Hi folks,

I would like to generate one net/reg output signal based on three
different trigger signals. I couldn't find a better way to generate
this signal but only using 3 registers+3 ANDs+ 1 3-wire OR or using
state machine required 3 register and a lot more combination circuit.
These two methods are the simplest implementation I can think of.

Is there any other even more simpler implementation to generate the
output?
Does anyone have any idea?


Required waveform:
http://picasaweb.google.com/cuthbert.kao/QuestionPics#5360915541643145538

Thanks,
Cuthbert

 

[Mike Treseler]

Cuthbert wrote:

I would like to generate one net/reg output signal based on three
different trigger signals. I couldn't find a better way to generate
this signal but only using 3 registers+3 ANDs+ 1 3-wire OR or using
state machine required 3 register and a lot more combination circuit.
These two methods are the simplest implementation I can think of.

Is there any other even more simpler implementation to generate the
output?

The waveforms imply three 2 bit shifters,
three AND gates for the D and not Q logic,
and one OR gate to collect the edge pulses.
Thats 3 flops and 4 gates.
A real registered output would require one more flop,
and would delay the Output one tick.

-- Mike Treseler

Required waveform:
http://picasaweb.google.com/cuthbert.kao/QuestionPics#5360915541643145538

 

[Cuthbert]

Hi Mr. Treseler,

Thanks for your reply.

The following is how I implemented. It seems just like what you said.
So, is this the simplest way to implement it?

// input A, B, and C
// output out

reg A_d;
reg B_d;
reg C_d;

wire A_p;
wire B_p;
wire C_p;

always@( posedge clk or negedge reset_n )
begin
if( !reset_n )
begin
A_d <= 1'b0;
B_d <= 1'b0;
C_d <= 1'b0;
end
else
begin
A_d <= A;
B_d <= B;
C_d <= C;
end
end

assign A_p = ( A && !A_d)? 1'b1 : 1'b0;
assign B_p = ( B && !B_d)? 1'b1 : 1'b0;
assign C_p = ( C && !C_d)? 1'b1 : 1'b0;
assign out = A_p | B_p | c_p;


On 7月22日, 上午1時24分, Mike Treseler <mtrese...@gmail.com> wrote:

The waveforms imply three 2 bit shifters,
three AND gates for the D and not Q logic,
and one OR gate to collect the edge pulses.
Thats 3 flops and 4 gates.
A real registered output would require one more flop,
and would delay the Output one tick.

        -- Mike Treseler

Required waveform:
http://picasaweb.google.com/cuthbert.kao/QuestionPics#536091554164314...

 

[Mike Treseler]

Cuthbert wrote:

Hi Mr. Treseler,
Thanks for your reply.
The following is how I implemented. It seems just like what you said.
So, is this the simplest way to implement it?

Your description is incomplete without a port specification.
Once completed, the module can be verified
using simulation and implemented using synthesis.
Start with the RTL viewer.
Good luck.

-- Mike Treseler

 

[Mike Treseler]

gabor wrote:

A point that I'm surprised Mike didn't make is that this only
works when the inputs are already synchronous to the clock as
in your diagram.

Edge detectors are often buried inside a synchronous design
to create clock enables for slow counters on a fast clock.

Standard practice for asynchronous input bits is
a two flop synchronizer, which in this case
would add two stages to each input shifter.
Only pulses wider than one clock cycle will be detected.

-- Mike Treseler

 

[gabor]

On Jul 22, 1:52 pm, Mike Treseler <mtrese...@gmail.com> wrote:

Cuthbert wrote:
Hi Mr. Treseler,
Thanks for your reply.
The following is how I implemented. It seems just like what you said.
So, is this the simplest way to implement it?

Your description is incomplete without a port specification.
Once completed, the module can be verified
using simulation and implemented using synthesis.
Start with the RTL viewer.
Good luck.

 -- Mike Treseler

A point that I'm surprised Mike didn't make is that this only
works when the inputs are already synchronous to the clock as
in your diagram. For asynchronous inputs, this method of
edge detection won't work when the input changes just before
the clock leading to a near-zero length pulse. For async
inputs you need another flip-flop prior to your circuit
and then the pulse is somewhat delayed.

Regards,
Gabor